Patents by Inventor Kazuhide Kumakura

Kazuhide Kumakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230261138
    Abstract: A light-emitting element includes: a light emitting layer formed of an i-type layered nitride semiconductor; a first semiconductor layer that is disposed on one surface of the light emitting layer, and is formed of a p-type layered nitride semiconductor or p-type diamond; and a second semiconductor layer that is disposed on the other surface of the light emitting layer, and is formed of an n-type layered nitride semiconductor.
    Type: Application
    Filed: July 13, 2020
    Publication date: August 17, 2023
    Inventors: Kazuyuki Hirama, Yoshitaka Taniyasu, Kazuhide Kumakura
  • Publication number: 20230101293
    Abstract: A buffer layer formed on a substrate, a base layer formed on the buffer layer, and a channel layer formed on the base layer are provided. The base layer includes AlxGa1-xN(0<x?1) and the composition x of Al decreases in accordance with increasing approach of the composition x to the channel layer in a thickness direction. The channel layer includes AlyGa1-yN(0<y?1) and the composition y of Al decreases in accordance with increasing approach of the composition y to the base layer in a thickness direction.
    Type: Application
    Filed: March 17, 2020
    Publication date: March 30, 2023
    Inventors: Masanobu Hiroki, Kazuhide Kumakura
  • Publication number: 20220059723
    Abstract: A p-type semiconductor layer includes a plurality of unit semiconductor layers, and each of the plurality of unit semiconductor layers includes a p-type nitride semiconductor whose main surface is a polar surface or a semi-polar surface. The nitride semiconductor constituting the unit semiconductor layer includes nitrogen and two or more elements, and each of the plurality of unit semiconductor layers has a composition changing in a stacking direction such that, for example, a lattice constant in a c-axis direction increases in a c-axis positive direction.
    Type: Application
    Filed: February 10, 2020
    Publication date: February 24, 2022
    Applicant: Nippon Telegraph and Telephone Corporation
    Inventors: Kazuaki Ebata, Yoshitaka Taniyasu, Kazuhide Kumakura
  • Publication number: 20210272794
    Abstract: First, in a first step, a semiconductor layer that is constituted by a nitride semiconductor and includes a group V polar surface as a main surface is formed. Next, in a second step, nitrogen atoms at the surface of the semiconductor layer are substituted with a group VI element that is any of oxygen, sulfur, selenium, and tellurium. Next, in a third step, a layered material layer is formed through epitaxial growth of a layered material on the semiconductor layer at which nitrogen atoms are substituted with the group VI element.
    Type: Application
    Filed: June 28, 2019
    Publication date: September 2, 2021
    Inventors: Koji Onomitsu, Tetsuya Akasaka, Masanobu Hiroki, Junichi Nishinaka, Kazuhide Kumakura
  • Patent number: 9219111
    Abstract: A nitride semiconductor structure of the present invention is obtained by growing an h- or t-BN thin film (12) and a wurtzite-structure AlxGa1-xN (x>0) thin film (14) as buffer layers and forming a single-crystal wurtzite-structure AlGaInBN thin film (13) thereon. While GaN, AlGaN, AlN, and the like have the wurtzite structure with sp3 bonds, h-BN or t-BN has the graphite structure with sp2 bonds, and has a completely different crystal structure. Accordingly, it has heretofore not been considered that a wurtzite-structure AlGaInBN thin film can be grown on a graphite-structure h-BN thin film. However, when a wurtzite-structure AlxGa1-xN (x>0) thin film (14) is formed as a buffer layer on a graphite-structure boron nitride thin film (12), a wurtzite-structure AlGaInBN (13) nitride semiconductor structure such as GaN can be grown on the buffer layer.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: December 22, 2015
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Yasuyuki Kobayashi, Kazuhide Kumakura, Tetsuya Akasaka, Toshiki Makimoto
  • Publication number: 20140145147
    Abstract: A nitride semiconductor structure of the present invention is obtained by growing an h- or t-BN thin film (12) and a wurtzite-structure AlxGa1-xN (x>0) thin film (14) as buffer layers and forming a single-crystal wurtzite-structure AlGaInBN thin film (13) thereon. While GaN, AlGaN, AlN, and the like have the wurtzite structure with sp3 bonds, h-BN or t-BN has the graphite structure with sp2 bonds, and has a completely different crystal structure. Accordingly, it has heretofore not been considered that a wurtzite-structure AlGaInBN thin film can be grown on a graphite-structure h-BN thin film. However, when a wurtzite-structure AlxGa1-xN (x>0) thin film (14) is formed as a buffer layer on a graphite-structure boron nitride thin film (12), a wurtzite-structure AlGaInBN (13) nitride semiconductor structure such as GaN can be grown on the buffer layer.
    Type: Application
    Filed: September 5, 2012
    Publication date: May 29, 2014
    Inventors: Yasuyuki Kobayashi, Kazuhide Kumakura, Tetsuya Akasaka, Toshiki Makimoto
  • Patent number: 7804106
    Abstract: A nitride semiconductor structure is provided which greatly improves ohmic characteristics by repairing process damage by regrowing an indium-containing p-type nitride semiconductor on a p-type nitride semiconductor having the process damage. In addition, a nitride semiconductor bipolar transistor is provided which can greatly improve its current gain and offset voltage. The structure includes an indium-containing p-type nitride semiconductor layer on a p-type nitride semiconductor processed by etching. The bipolar transistor, which has a base layer composed of a p-type nitride semiconductor, has an indium-containing p-type InGaN base layer regrown on a surface of a p-type InGaN base layer exposed by etching an emitter layer.
    Type: Grant
    Filed: January 6, 2004
    Date of Patent: September 28, 2010
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Toshiki Makimoto, Kazuhide Kumakura, Naoki Kobayashi
  • Patent number: 7244520
    Abstract: A substrate for growth of nitride semiconductor capable of obtaining a high-quality nitride semiconductor crystal layer is provided. A substrate for growth of nitride semiconductor for growth of a nitride semiconductor layer on a sapphire substrate (1) according to one embodiment of the invention is provided with an Al2O3 layer (2) as separately provided on the sapphire substrate (1), an AlON layer (3) which is the first layer, and an AlN layer (4) which is the second layer. With respect to the first layer and the second layer, the AlON layer (3) and the AlN layer (4) are deposited on the Al2O3 layer (2) in this order.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: July 17, 2007
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Kazuhide Kumakura, Masanobu Hiroki, Toshiki Makimoto
  • Publication number: 20060051554
    Abstract: A substrate for growth of nitride semiconductor capable of obtaining a high-quality nitride semiconductor crystal layer is provided. A substrate for growth of nitride semiconductor for growth of a nitride semiconductor layer on a sapphire substrate (1) according to one embodiment of the invention is provided with an Al2O3 layer (2) as separately provided on the sapphire substrate (1), an AlON layer (3) which is the first layer, and an AlN layer (4) which is the second layer. With respect to the first layer and the second layer, the AlON layer (3) and the AlN layer (4) are deposited on the Al2O3 layer (2) in this order.
    Type: Application
    Filed: August 11, 2004
    Publication date: March 9, 2006
    Inventors: Kazuhide Kumakura, Masanobu Hiroki, Toshiki Makimoto
  • Publication number: 20050224831
    Abstract: A nitride semiconductor structure is provided which greatly improves ohmic characteristics by repairing process damage by regrowing an indium-containing p-type nitride semiconductor on a p-type nitride semiconductor having the process damage. In addition, a nitride semiconductor bipolar transistor is provided which can greatly improve its current gain and offset voltage. The structure includes an indium-containing p-type nitride semiconductor layer on a p-type nitride semiconductor processed by etching. The bipolar transistor, which has a base layer composed of a p-type nitride semiconductor, has an indium-containing p-type InGaN base layer regrown on a surface of a p-type InGaN base layer exposed by etching an emitter layer.
    Type: Application
    Filed: January 6, 2004
    Publication date: October 13, 2005
    Inventors: Toshiki Makimoto, Kazuhide Kumakura, Naoki Kobayashi
  • Patent number: 6667498
    Abstract: A transistor structure is implemented which can achieve high current gain by causing electrons injected from an emitter to reach a collector. An InGaN graded layer, which is interposed between a p-type InGaN layer and an n-type GaN layer, includes an In composition that varies from 0% to 10%. A bandgap of the thin film structure is gradually reduced from the substrate side to the surface side. An AlN buffer layer is grown on an SiC substrate by 100 nm thick, followed by growing a Si-doped GaN layer used for forming an ohmic electrode. A Si-doped GaN layer (n-type GaN layer) is grown thereon, followed by growing an InGaN layer whose In composition is varied, and by growing, an Mg-doped InGaN (p-type GaN layer), thereby fabricating a heterojunction diode.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: December 23, 2003
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Toshiki Makimoto, Kazuhide Kumakura, Naoki Kobayashi
  • Publication number: 20020195619
    Abstract: A transistor structure is implemented which can achieve high current gain by causing electrons injected from an emitter to reach a collector. An InGaN graded layer, which is interposed between a p-type InGaN layer and an n-type GaN layer, includes an In composition that varies from 0% to 10%. A bandgap of the thin film structure is gradually reduced from the substrate side to the surface side. An AlN buffer layer is grown on an SiC substrate by 100 nm thick, followed by growing a Si-doped GaN layer used for forming an ohmic electrode. A Si-doped GaN layer (n-type GaN layer) is grown thereon, followed by growing an InGaN layer whose In composition is varied, and by growing, an Mg-doped InGaN (p-type GaN layer), thereby fabricating a heterojunction diode.
    Type: Application
    Filed: June 5, 2002
    Publication date: December 26, 2002
    Applicant: Nippon Telegraph and Telephone Corporation
    Inventors: Toshiki Makimoto, Kazuhide Kumakura, Naoki Kobayashi