Patents by Inventor Kazuhide Sumiyoshi

Kazuhide Sumiyoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230054259
    Abstract: A semiconductor device includes a substrate, a semiconductor stacking portion formed on the substrate, a silicon nitride passivation film covering the surface of the semiconductor stacking portion, and oxygen atoms existing at an interface between the silicon nitride passivation film and the semiconductor stacking portion. The semiconductor stacking portion includes a plurality of nitride semiconductor layers. The interfacial oxygen content at the passivation film and stacking portion interface is 0.6×1015 oxygen atoms/cm2 or less.
    Type: Application
    Filed: October 4, 2022
    Publication date: February 23, 2023
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kazuhide SUMIYOSHI, Masaya OKADA, Kazutaka INOUE, Takumi YONEMURA
  • Patent number: 11430653
    Abstract: A method of manufacturing a high electron mobility transistor in a furnace, the method including steps of: forming a first SiN film on a surface of a semiconductor stack consisting of a nitride semiconductor and including a barrier layer by a low pressure chemical vapor deposition method at a first furnace temperature of 700° C. or more and 900° C. or less; forming an interface oxide layer on the first SiN film by moisture and oxygen in the furnace at a second furnace temperature of 700° C. or more and 900° C. or less and a furnace pressure to 1 Pa or lower; and forming a second SiN film on the interface oxide layer by the low pressure chemical vapor deposition method at a third furnace temperature of 700° C. or more and 900° C. or less.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 30, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takuji Yamamura, Kenya Nishiguchi, Kazuhide Sumiyoshi
  • Publication number: 20210104395
    Abstract: A method of manufacturing a high electron mobility transistor, comprising steps of: forming a first SiN film on a surface of a semiconductor stack consisting of a nitride semiconductor and including a barrier layer by a low pressure chemical vapor deposition method at a first furnace temperature of 700° C. or more and 900° C. or less; forming an interface oxide layer on the first SiN film by moisture and oxygen in the furnace at a second furnace temperature of 700° C. or more and 900° C. or less and a furnace pressure to 1 Pa or lower; and forming a second SiN film on the interface oxide layer by the low pressure chemical vapor deposition method at a third furnace temperature of 700° C. or more and 900° C. or less.
    Type: Application
    Filed: September 29, 2020
    Publication date: April 8, 2021
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takuji YAMAMURA, Kenya NISHIGUCHI, Kazuhide SUMIYOSHI
  • Publication number: 20210066065
    Abstract: A method of forming a silicon nitride passivation film on a nitride semiconductor layer is comprising steps of, introducing a substrate including the nitride semiconductor layer into a reaction furnace, replacing an atmosphere in the reaction furnace from air to an ammonia (NH3) atmosphere or to a hydrogen (H2) atmosphere, raising a temperature in the reaction furnace to a first temperature, maintaining both the temperature in the reaction furnace at the first temperature and the atmosphere in the reaction furnace at the NH3 atmosphere or the H2 atmosphere for three minutes or more, lowering the temperature in the reaction furnace to a second temperature lower than the first temperature, and forming the silicon nitride passivation film by supplying dichlorosilane (SiH2Cl2) into the reaction furnace under the first pressure of 100 Pa or less in the reaction furnace.
    Type: Application
    Filed: September 3, 2020
    Publication date: March 4, 2021
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kazuhide SUMIYOSHI, Masaya OKADA, Kazutaka INOUE, Takumi YONEMURA
  • Patent number: 10832905
    Abstract: A low pressure chemical vapor deposition (LPCVD) technique for nitride semiconductor materials includes steps of: setting a temperature in a furnace to be 750 to 900° C.; substituting an atmosphere in the furnace to ammonia (NH3); depositing a SiN film at an initial pressure by supplying di-chloro-silane (SiH2Cl2); and subsequently depositing the SiN film at a deposition pressure that is higher than the initial pressure. The invention has a feature that the initial pressure is at least higher than 60% of the deposition pressure.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: November 10, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Kazuhide Sumiyoshi
  • Patent number: 10741384
    Abstract: A process of depositing a silicon nitride (SiN) film on a nitride semiconductor layer is disclosed. The process includes steps of: (a) loading an epitaxial substrate including the nitride semiconductor layer into a reaction furnace at a first temperature and converting an atmosphere in the furnace into nitrogen (N2); (b) raising the temperature in the furnace to a second temperature while keeping pressure in the furnace at a first pressure higher than 30 kPa; (c) converting the atmosphere in the furnace to ammonia (NH3) at the second temperature; and (d) beginning the deposition by supplying SiH2Cl2 as a source gas for silicon (Si) at a second pressure lower than 100 Pa. A feature of the process is that a time span from when the temperature in the furnace reaches the critical temperature to the supply of SiH2Cl2 is shorter than 20 minutes, where the first pressure becomes the equilibrium pressure at the critical temperature.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 11, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Kazuhide Sumiyoshi
  • Patent number: 10566184
    Abstract: A process of forming a silicon nitride film on a nitride semiconductor layer as a passivation film is disclosed. The process first sets a temperature lower than 500° C. to load into a growth reactor, a wafer that provides the nitride semiconductor layer thereon. Then, the process raises the temperature to a deposition temperature higher than 750° C. while replacing the atmosphere in the reactor with pure ammonia (NH3), or a mixed gas of NH3 and N2 with a NH3 partial pressure greater than 0.2, and sets the pressure higher than 3 kPa. Finally, with the pressure lower than 100 Pa and di-chloro-silane (SiH2Cl2) supplied, the SiN is deposited on the nitride semiconductor layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 18, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Kazuhide Sumiyoshi
  • Publication number: 20190172706
    Abstract: A sequence of a low pressure chemical vapor deposition (LPCVD) technique for nitride semiconductor materials is disclosed. The sequence comprises steps of: setting a temperature in a furnace to be 750 to 900° C.; substituting an atmosphere in the furnace to ammonia (NH3); depositing a SiN film at an initial pressure by supplying di-chloro-silane (SiH2Cl2); subsequently depositing the SiN film at a deposition pressure that is higher than the initial pressure. The sequence of the invention has a feature that the initial pressure is at least higher than 60% of the deposition pressure.
    Type: Application
    Filed: December 5, 2018
    Publication date: June 6, 2019
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Kazuhide SUMIYOSHI
  • Patent number: 10283609
    Abstract: A nitride semiconductor device is disclosed, where the nitride semiconductor device is a type of field effect transistor having a gate electrode and an insulating film covering the gate electrode. The gate electrode has stacked metals of nickel (Ni) and gold (Au), while, the insulating film is made of silicon nitride (Si). A feature of the gate electrode of the present invention is that the nickel layer contains silicon (Si) atoms at an atomic concentration from 0.01 at % to 10 at %.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: May 7, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Kazuhide Sumiyoshi
  • Publication number: 20190103264
    Abstract: A process of depositing a silicon nitride (SiN) film on a nitride semiconductor layer is disclosed. The process includes steps of: (a) loading an epitaxial substrate including the nitride semiconductor layer into a reaction furnace at a first temperature and converting an atmosphere in the furnace into nitrogen (N2); (b) raising a temperature in the furnace to a second temperature keeping a pressure in the furnace higher than 30 kPa; (c) converting the atmosphere in the furnace to ammonia (NH3) at the second temperature; and (d) beginning the deposition by supplying SiH2Cl2 as a source gas for silicon (Si) at a second pressure lower than 100 Pa. A feature of the process is that a time span from the temperature in the furnace reaches the critical temperature to the supply of SiH2Cl2 is shorter than 20 minutes, where the first pressure becomes the equilibrium pressure at the critical temperature.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 4, 2019
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Kazuhide SUMIYOSHI
  • Publication number: 20180286661
    Abstract: A process of forming a silicon nitride film on a nitride semiconductor layer as a passivation film is disclosed. The process first set a temperature lower than 500° C. to load a wafer that provides the nitride semiconductor layer thereon. Then, the process raises a temperature to a deposition temperature higher than 750° C. as replacing an atmosphere to a pure ammonia (NH3), or a mixed gas of NH3 and N2 with a NH3 partial pressure greater than 0.2, and setting a pressure higher than 3 kPa. Finally, decompressing the atmosphere lower than 100 Pa and supplying di-chloro-silane (SiH2Cl2), the SiN is deposited on the nitride semiconductor layer.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 4, 2018
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Kazuhide SUMIYOSHI
  • Publication number: 20180090584
    Abstract: A nitride semiconductor device is disclosed, where the nitride semiconductor device type of a field effect transistor having a gate electrode and an insulating film covering the gate electrode. The gate electrode has stacked metals of nickel (Ni) and gold (Au), while, the insulating film is made of silicon nitride (Si). A feature of the gate electrode of the present invention is that the nickel layer contains or dopes silicon (Si) atoms by an atomic concentration from 0.01 at % to 10 at %.
    Type: Application
    Filed: September 20, 2017
    Publication date: March 29, 2018
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Kazuhide SUMIYOSHI
  • Patent number: 9425348
    Abstract: In a group III nitride semiconductor device according to one aspect of the present invention, in a p-type group III nitride semiconductor region formed on a semi-polar plane substrate, the concentration of hydrogen (H) contained in the p-type group III nitride semiconductor region is 25% or less of the concentration of a p-type dopant therein, and the concentration of oxygen contained in the p-type group III nitride semiconductor region is 5×1017 atoms/cm3 or lower, and an angle between a normal axis of a primary surface of the semi-polar plane substrate and a c-axis of the semi-polar plane substrate is not lower than 45 degrees and not higher than 80 degrees or not lower than 100 degrees and not higher than 135 degrees in a waveguide axis direction of the group III nitride semiconductor device.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: August 23, 2016
    Assignees: Summitomo Electric Industries, Ltd., SONY CORPORATION
    Inventors: Nobuhiro Saga, Shinji Tokuyama, Kazuhide Sumiyoshi, Takashi Kyono, Koji Katayama, Tatsushi Hamaguchi, Katsunori Yanashima
  • Publication number: 20150115312
    Abstract: In a group III nitride semiconductor device according to one aspect of the present invention, in a p-type group III nitride semiconductor region formed on a semi-polar plane substrate, the concentration of hydrogen (H) contained in the p-type group III nitride semiconductor region is 25% or less of the concentration of a p-type dopant therein, and the concentration of oxygen contained in the p-type group III nitride semiconductor region is 5×1017 atoms/cm3 or lower, and an angle between a normal axis of a primary surface of the semi-polar plane substrate and a c-axis of the semi-polar plane substrate is not lower than 45 degrees and not higher than 80 degrees or not lower than 100 degrees and not higher than 135 degrees in a waveguide axis direction of the group III nitride semiconductor device.
    Type: Application
    Filed: October 22, 2014
    Publication date: April 30, 2015
    Inventors: Nobuhiro Saga, Shinji Tokuyama, Kazuhide Sumiyoshi, Takashi Kyono, Koji Katayama, Tatsushi Hamaguchi, Katsunori Yanashima
  • Patent number: 8507305
    Abstract: A III-nitride semiconductor laser device is provided with a laser structure and an electrode. The laser structure includes a support base which includes a hexagonal III-nitride semiconductor and a semipolar primary surface, and a semiconductor region provided on the semipolar primary surface. The electrode is provided on the semiconductor region. The semiconductor region includes a first cladding layer of a first conductivity type GaN-based semiconductor, a second cladding layer of a second conductivity type GaN-based semiconductor, and an active layer provided between the first cladding layer and the second cladding layer.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: August 13, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yusuke Yoshizumi, Yohei Enya, Takashi Kyono, Takamichi Sumitomo, Nobuhiro Saga, Masahiro Adachi, Kazuhide Sumiyoshi, Shinji Tokuyama, Shimpei Takagi, Takatoshi Ikegami, Masaki Ueno, Koji Katayama
  • Patent number: 8502310
    Abstract: Provided is a III nitride semiconductor electronic device having a structure capable of reducing leakage current. A laminate 11 includes a substrate 13 and a III nitride semiconductor epitaxial film 15. The substrate 13 is made of a III nitride semiconductor having a carrier concentration of more than 1×1018 cm?3. The epitaxial structure 15 includes a III nitride semiconductor epitaxial film 17. A first face 13a of the substrate 13 is inclined at an angle ? of more than 5 degrees with respect to an axis Cx extending in a direction of the c-axis. A normal vector VN and a c-axis vector VC make the angle ?. The III nitride semiconductor epitaxial film 17 includes first, second and third regions 17a, 17b and 17c arranged in order in a direction of a normal to the first face 13a. A dislocation density of the third region 17c is smaller than that of the first region 17a. A dislocation density of the second region 17b is smaller than that of the substrate 13.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: August 6, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiromu Shiomi, Kazuhide Sumiyoshi, Yu Saitoh, Makoto Kiyama
  • Patent number: 8349078
    Abstract: The present method of forming a nitride semiconductor epitaxial layer includes the steps of growing at least one layer of nitride semiconductor epitaxial layer on a nitride semiconductor substrate having a dislocation density lower than or equal to 1×107 cm?2 with a chemical decomposition layer interposed therebetween, the chemical decomposition layer being chemically decomposed at least with either a gas or an electrolytic solution, and decomposing the chemical decomposition layer at least with either the gas or the electrolytic solution at least either during or after the step of growing the nitride semiconductor epitaxial layer, thereby separating the nitride semiconductor epitaxial layer from the nitride semiconductor substrate. A high-quality nitride semiconductor epitaxial layer suffering less damage when separated from the nitride semiconductor substrate is thereby formed.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: January 8, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiromu Shiomi, Yu Saitoh, Kazuhide Sumiyoshi, Akihiro Hachigo, Makoto Kiyama, Seiji Nakahata
  • Publication number: 20120258557
    Abstract: A III-nitride semiconductor laser device is provided with a laser structure and an electrode. The laser structure includes a support base which includes a hexagonal III-nitride semiconductor and a semipolar primary surface, and a semiconductor region provided on the semipolar primary surface. The electrode is provided on the semiconductor region. The semiconductor region includes a first cladding layer of a first conductivity type GaN-based semiconductor, a second cladding layer of a second conductivity type GaN-based semiconductor, and an active layer provided between the first cladding layer and the second cladding layer.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 11, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Yusuke Yoshizumi, Yohei Enya, Takashi Kyono, Takamichi Sumitomo, Nobuhiro Saga, Masahiro Adachi, Kazuhide Sumiyoshi, Shinji Tokuyama, Shimpei Takagi, Takatoshi Ikegami, Masaki Ueno, Koji Katayama
  • Publication number: 20120104556
    Abstract: The present power device includes a metal-made support substrate, and a group III nitride conductive layer, a group III nitride active layer and an electrode successively formed on one main surface side of the metal-made support substrate. In addition, the present method for manufacturing a power device includes the steps of preparing a conductive-layer-joined metal-made support substrate in which a group III nitride conductive layer is joined to a metal-made support substrate, forming a group III nitride active layer on the group III nitride conductive layer, and forming an electrode on the group III nitride active layer. Thus, an inexpensive power device low in on-resistance and a method for manufacturing the same can be provided.
    Type: Application
    Filed: October 27, 2010
    Publication date: May 3, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Makoto KIYAMA, Hiromu SHIOMI, Kazuhide SUMIYOSHI, Akihiro HACHIGO
  • Publication number: 20110223749
    Abstract: The present method of forming a nitride semiconductor epitaxial layer includes the steps of growing at least one layer of nitride semiconductor epitaxial layer on a nitride semiconductor substrate having a dislocation density lower than or equal to 1×107 cm?2 with a chemical decomposition layer interposed therebetween, the chemical decomposition layer being chemically decomposed at least with either a gas or an electrolytic solution, and decomposing the chemical decomposition layer at least with either the gas or the electrolytic solution at least either during or after the step of growing the nitride semiconductor epitaxial layer, thereby separating the nitride semiconductor epitaxial layer from the nitride semiconductor substrate. A high-quality nitride semiconductor epitaxial layer suffering less damage when separated from the nitride semiconductor substrate is thereby formed.
    Type: Application
    Filed: October 27, 2010
    Publication date: September 15, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiromu SHIOMI, Yu Saitoh, Kazuhide Sumiyoshi, Akihiro Hachigo, Makoto Kiyama, Seiji Nakahata