Patents by Inventor Kazuhide Takamura

Kazuhide Takamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10916557
    Abstract: According to one embodiment, the first electrode layer includes a first portion and a second portion thicker than the first portion. The second electrode layer includes a third portion and a fourth portion thicker than the third portion. The fourth portion is provided on a lower level side of the second portion. The fourth portion has a level difference in a staircase configuration between the fourth portion and the second portion. The fourth portion protrudes along a first direction further than an edge of the second portion. The third electrode layer is provided between the first electrode layer and the third portion. The third electrode layer has an edge receding further than the edge of the second portion of the first electrode layer. The receding is in a reverse direction of a protruding direction of the fourth portion of the second electrode layer.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: February 9, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shunpei Takeshita, Namiki Yoshikawa, Kazuhide Takamura, Naoki Yamamoto
  • Patent number: 10804286
    Abstract: According to one embodiment, a semiconductor device includes: a stack body including an insulator, a first conductor and a second conductor stacked stepwise by interposing the insulator and electrically disconnected from each other; and a first contact plug which reaches the first conductor from a region above the stack body. The first conductor includes a first portion positioned below the insulator, a second portion positioned above the insulator, and a third portion that electrically connects the first portion of the first conductor and the second portion of the first conductor. The third portion of the first conductor is provided in an opening formed on the insulator.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuhide Takamura, Takuya Inatsuka
  • Publication number: 20190348431
    Abstract: According to one embodiment, the first electrode layer includes a first portion and a second portion thicker than the first portion. The second electrode layer includes a third portion and a fourth portion thicker than the third portion. The fourth portion is provided on a lower level side of the second portion. The fourth portion has a level difference in a staircase configuration between the fourth portion and the second portion. The fourth portion protrudes along a first direction further than an edge of the second portion. The third electrode layer is provided between the first electrode layer and the third portion. The third electrode layer has an edge receding further than the edge of the second portion of the first electrode layer. The receding is in a reverse direction of a protruding direction of the fourth portion of the second electrode layer.
    Type: Application
    Filed: September 6, 2018
    Publication date: November 14, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Shunpei TAKESHITA, Namiki YOSHIKAWA, Kazuhide TAKAMURA, Naoki YAMAMOTO
  • Publication number: 20190280004
    Abstract: According to one embodiment, a semiconductor device includes: a stack body including an insulator, a first conductor and a second conductor stacked stepwise by interposing the insulator and electrically disconnected from each other; and a first contact plug which reaches the first conductor from a region above the stack body. The first conductor includes a first portion positioned below the insulator, a second portion positioned above the insulator, and a third portion that electrically connects the first portion of the first conductor and the second portion of the first conductor. The third portion of the first conductor is provided in an opening formed on the insulator.
    Type: Application
    Filed: August 24, 2018
    Publication date: September 12, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Kazuhide TAKAMURA, Takuya INATSUKA
  • Patent number: 8946809
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor memory device. The method includes forming a first stopper film forming a lower gate layer, making a recess in the lower gate layer, filling a sacrificial film into the recess, forming a second stopper film, making an opening in the second stopper film, forming a stacked body. The stacked body includes electrode films and insulating films. The method includes, making a slit in the stacked body, making a hole in the stacked body, removing the sacrificial film via the hole, forming a memory film including a charge storage film. The method includes forming a channel body on a side wall of the memory film. An etching rate of the first stopper film and the second stopper film is lower than an etching rate of the electrode films and the insulating films.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: February 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhide Takamura, Ryota Katsumata, Masaru Kidoh, Yoshihiro Uozumi, Daigo Ichinose, Toru Matsuda
  • Publication number: 20140284691
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor memory device. The method includes forming a first stopper film forming a lower gate layer, making a recess in the lower gate layer, filling a sacrificial film into the recess, forming a second stopper film, making an opening in the second stopper film, forming a stacked body. The stacked body includes electrode films and insulating films. The method includes, making a slit in the stacked body, making a hole in the stacked body, removing the sacrificial film via the hole, forming a memory film including a charge storage film. The method includes forming a channel body on a side wall of the memory film. An etching rate of the first stopper film and the second stopper film is lower than an etching rate of the electrode films and the insulating films.
    Type: Application
    Filed: September 4, 2013
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuhide Takamura, Ryota Katsumata, Masaru Kidoh, Yoshihiro Uozumi, Daigo Ichinose, Toru Matsuda