Abstract: A semiconductor integrated circuit reads data from a memory, which stores the data including a data portion and a parity bit, and makes an error correction to the data. The semiconductor integrated circuit includes a memory controller for reading the data from the memory; and an error correction controller having an error correction circuit having the ability to correct a predetermined number of bits of errors. The error correction controller applies an error correction to the read data by the error correction circuit, and determines whether all errors contained in the data are corrected, based on the data portion and the parity bit of the data after the error correction. When not all the errors contained in the data are determined to be corrected, the error correction controller applies an error correction by the error correction circuit, while sequentially inverting the data value of each bit of the data.

Abstract: A semiconductor integrated circuit reads data from a memory, which stores the data including a data portion and a parity bit, and makes an error correction to the data. The semiconductor integrated circuit includes a memory controller for reading the data from the memory; and an error correction controller having an error correction circuit having the ability to correct a predetermined number of bits of errors. The error correction controller applies an error correction to the read data by the error correction circuit, and determines whether all errors contained in the data are corrected, based on the data portion and the parity bit of the data after the error correction. When not all the errors contained in the data are determined to be corrected, the error correction controller applies an error correction by the error correction circuit, while sequentially inverting the data value of each bit of the data.

Abstract: A USB device set includes a first USB device, which is operable both as a host device and as a peripheral device; and a second USB device, which is operable both as a host device, and as a peripheral device. Each of the first and second USB devices includes: a first memory region storing device drivers of other USB devices; a second memory region storing its own device driver; and a device driver control circuit, which can update device drivers stored at least in the first memory region. In one of the first and second USB devices that is operating as a peripheral device, the device driver control circuit receives information on the device driver of the other USB device, operating as a host device, when the first and second USB devices are firstly connected to each other; and updates the first memory region in accordance with the received information.

Abstract: As a data bus control enable signal is set to “H,” a PMOS turns on when a bi-directional bus is not in use (i.e., when a data bus active signal is “L”), so that the bi-directional bus is pulled down through a pull-down resistor. When the data bus control enable signal is set to “L,” the PMOS turns off, thus holding the bi-directional bus in a high-impedance state. By setting the data bus control enable signal in accordance with the specifications of a peripheral device connected thereto, the state of the bi-directional bus can be arbitrarily set when it is inactive.

Abstract: As a data bus control enable signal is set to “H,” a PMOS turns on when a bi-directional bus is not in use (i.e., when a data bus active signal is “L”), so that the bi-directional bus is pulled down through a pull-down resistor. When the data bus control enable signal is set to “L,” the PMOS turns off, thus holding the bi-directional bus in a high-impedance state. By setting the data bus control enable signal in accordance with the specifications of a peripheral device connected thereto, the state of the bi-directional bus can be arbitrarily set when it is inactive.

Abstract: A USB device set includes a first USB device, which is operable both as a host device and as a peripheral device; and a second USB device, which is operable both as a host device, and as a peripheral device. Each of the first and second USB devices includes: a first memory region storing device drivers of other USB devices; a second memory region storing its own device driver; and a device driver control circuit, which can update device drivers stored at least in the first memory region. In one of the first and second USB devices that is operating as a peripheral device, the device driver control circuit receives information on the device driver of the other USB device, operating as a host device, when the first and second USB devices are firstly connected to each other; and updates the first memory region in accordance with the received information.

Abstract: A process controller 130 and clock controller 190 are used to detect transfer rates when performing data write and read operations involving memories 180-1 to 180-n for recording data. The clock controller 190 frequency-divides clock signals generated by an oscillator unit 191, thereby generating a plurality of frequency-divided clocks having different frequencies. One of the frequency-divided clocks is selected, according to the transfer rate detection results, and used as the operating clock for an interface unit 110, the process controller 130, a buffer unit 140, and a transfer controller 150. By altering the operating speeds of the circuits 110, 140, and 150, according to the data transfer rate, power consumption can be reduced.

Abstract: In the semiconductor memory device relating to the present invention, the memory is divided into a plurality of blocks having a plurality of sectors and stores user data in units of sectors. When writing one sector of user data, the controller converts the logical block address to a physical block address using the address table. The controller selects one unused block and writes one sector of user data to this unused block. When user data are stored in this unused block, all data in this block are deleted before data are written thereto. Next, the controller reads data corresponding to other sectors from a block corresponding to the physical block address discussed above and copies this data in order to an unused block. When the writing ends, the control portion overwrites the address table so that the physical address of this unused block is assigned to the logical block address discussed above.

Abstract: A storage device uses an inventive alternate processing method for accommodating defective sectors of the storage device. The storage device includes a host interface, an alternate process controller which controls the storage and transfer of user data in and among the components of the apparatus, a memory which has a user sector area, an alternate information area, and a spare sector area, and a buffer memory which may be a part of the controller. User data addressed to normal sectors of memory are stored directly in the user sector area. When user data is addressed to a defective sector, the controller performs alternate processing and temporarily stores the data in the buffer memory. A plurality of user data sectors stored in the buffer memory are then written by the controller at one time to the spare sector area of memory using address data in the alternate information area.