Patents by Inventor Kazuhiko Eguchi

Kazuhiko Eguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096243
    Abstract: A novel display panel that is highly convenient, useful, or reliable is provided. The display panel includes a display region, a first support, and a second support, the display region includes a first region, a second region, and a third region, the first region and the second region each have a belt-like shape extending in one direction, and the third region is sandwiched between the first region and the second region. The first support overlaps with the first region and is less likely to be warped than the third region, and the second support overlaps with the second region and is less likely to be warped than the third region. The second support can pivot on an axis extending in the one direction with respect to the first support.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Inventors: Shingo EGUCHI, Taiki NONAKA, Daiki NAKAMURA, Nozomu SUGISAWA, Kazuhiko FUJITA, Shunpei YAMAZAKI
  • Patent number: 6622292
    Abstract: The optimization algorithm candidate of a plurality of circuit blocks given with the logic circuit description based on the hardware description language is determined considering the Hamming distance of circuit block (S1 to S3). The common circuit blocks of the optimization algorithm candidate determined in the first process are then grouped considering the coupling degree among circuit blocks (S4 to S6). Result of grouping is the result for the circuit blocks having apparent characteristic in the algorithm candidate and coupling degree and the circuit blocks having uncertain characteristics are also left. In view of optimizing the grouping for the circuit blocks having uncertain characteristics, the grouping of a plurality of circuit blocks is optimized with the hereditary algorithm by reflecting the result of grouping on the initial condition.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: September 16, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Ko Miyazaki, Kazuhiko Eguchi, Tadaaki Tanimoto
  • Publication number: 20020032894
    Abstract: The optimization algorithm candidate of a plurality of circuit blocks given with the logic circuit description based on the hardware description language is determined considering the Hamming distance of circuit block (S1 to S3). The common circuit blocks of the optimization algorithm candidate determined in the first process are then grouped considering the coupling degree among circuit blocks (S4 to S6). Result of grouping is the result for the circuit blocks having apparent characteristic in the algorithm candidate and coupling degree and the circuit blocks having uncertain characteristics are also left. In view of optimizing the grouping for the circuit blocks having uncertain characteristics, the grouping of a plurality of circuit blocks is optimized with the hereditary algorithm by reflecting the result of grouping on the initial condition.
    Type: Application
    Filed: August 6, 2001
    Publication date: March 14, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Ko Miyazaki, Kazuhiko Eguchi, Tadaaki Tanimoto