Patents by Inventor Kazuhiko Egusa

Kazuhiko Egusa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device with varying dummy via-hole plug density
    Patent number: 7470981
    Abstract: The present invention is concerned with a method for producing a semiconductor device wherein lower-layer wirings and upper-layer wirings are formed with an interlayer insulating film therebetween, and the lower-layer wirings are electrically connected to the upper-layer wirings via via-hole plugs. Over a semiconductor substrate, the interlayer insulating film is formed to cover the lower-layer wirings. In the interlayer insulating film, via-holes for exposing surfaces of the lower-layer wirings are formed, and simultaneously, in a region of the interlayer insulating film where no via-holes exist, dummy via-holes which are not deep enough to reach down to the lower-layer wirings are formed. The dummy via-holes are formed in such a manner that the density of the dummy via-holes gradually decreases from a region where the via-holes are formed. Over the semiconductor substrate, a metal layer is formed to fill the via-holes and the dummy via-holes.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: December 30, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazuhiko Egusa
  • Semiconductor device and method for producing same
    Publication number: 20060065981
    Abstract: The present invention is concerned with a method for producing a semiconductor device wherein lower-layer wirings and upper-layer wirings are formed with an interlayer insulating film therebetween, and the lower-layer wirings are electrically connected to the upper-layer wirings via via-hole plugs. Over a semiconductor substrate, the interlayer insulating film is formed to cover the lower-layer wirings. In the interlayer insulating film, via-holes for exposing surfaces of the lower-layer wirings are formed, and simultaneously, in a region of the interlayer insulating film where no via-holes exist, dummy via-holes which are not deep enough to reach down to the lower-layer wirings are formed. The dummy via-holes are formed in such a manner that the density of the dummy via-holes gradually decreases from a region where the via-holes are formed. Over the semiconductor substrate, a metal layer is formed to fill the via-holes and the dummy via-holes.
    Type: Application
    Filed: September 27, 2005
    Publication date: March 30, 2006
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Kazuhiko Egusa