Patents by Inventor Kazuhiko Fujimoto

Kazuhiko Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8487423
    Abstract: In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: July 16, 2013
    Assignee: Panasonic Corporation
    Inventors: Yoichi Matsumura, Chie Kabuo, Takako Ohashi, Tadafumi Kadota, Kazuhiko Fujimoto, Hirofumi Miyashita
  • Publication number: 20110260333
    Abstract: In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.
    Type: Application
    Filed: June 27, 2011
    Publication date: October 27, 2011
    Applicant: Panasonic Corporation
    Inventors: Yoichi MATSUMURA, Chie Kabuo, Takako Ohashi, Tadafumi Kadota, Kazuhiko Fujimoto, Hirofumi Miyashita
  • Publication number: 20110012260
    Abstract: To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.
    Type: Application
    Filed: September 28, 2010
    Publication date: January 20, 2011
    Applicant: Panasonic Corporation
    Inventors: Shinya TOKUNAGA, Mitsumi Ito, Nobufusa Iwanishi, Koichi Seko, Hiroaki Suzuki, Hiroyuki Tanaka, Yuichi Nishimura, Kazuhiko Fujimoto
  • Patent number: 7831949
    Abstract: To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: November 9, 2010
    Assignee: Panasonic Corporation
    Inventors: Shinya Tokunaga, Mitsumi Ito, Nobufusa Iwanishi, Koichi Seko, Hiroaki Suzuki, Hiroyuki Tanaka, Yuichi Nishimura, Kazuhiko Fujimoto
  • Publication number: 20090193374
    Abstract: As a method for considering the adverse influence of the stresses caused form the pad, two sorts of methods are provided. As one method, while delay variation values of cells caused by an adverse influence of stresses are calculated, the calculated delay variation values are applied to the cells so as to perform a timing analysis, and the like by considering the adverse influence of the stresses. Then, in order that a flip chip type LSI is designed by employing a result of the above-described analysis in such a manner that the adverse influence of the stresses applied from the pad is not given to vias, wiring lines, and cells located under the pad, such a physical structure that no via is arranged under the pad is employed.
    Type: Application
    Filed: January 12, 2009
    Publication date: July 30, 2009
    Inventors: Kazuhiko FUJIMOTO, Kenji Yokoyama, Takeya Fujino, Takako Ohashi, Hiromasa Fukazawa, Yohei Takagi, Kazuhisa Fujita
  • Publication number: 20080197449
    Abstract: A method is provided for designing a wiring structure of a wiring layer of a semiconductor integrated circuit device. The method includes a wire width detecting step of detecting a wire width of each wire in a wiring pattern of layout data, a wire identifying step of identifying a wire having a predetermined wire width or more based on a result of detection by the wire width detecting step, a wiring pitch detecting step of detecting a wiring pitch between the wire identified by the wire identifying step and another wire, and an air gap-forbidden region forming and removing step of forming or removing an air gap-forbidden region, depending on a result of detection by the wiring pitch detecting step.
    Type: Application
    Filed: February 21, 2008
    Publication date: August 21, 2008
    Inventors: Takayuki ARAKI, Junichi Shimada, Hirokazu Ogawa, Kazuhiko Fujimoto, Tsutomu Fujii, Takuya Yasui
  • Publication number: 20080022252
    Abstract: To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 24, 2008
    Inventors: Shinya Tokunaga, Mitsumi Ito, Nobufusa Iwanishi, Koichi Seko, Hiroaki Suzuki, Hiroyuki Tanaka, Yuichi Nishimura, Kazuhiko Fujimoto
  • Patent number: 7093222
    Abstract: A power supply wiring method for a semiconductor integrated circuit is disclosed in which power supply provision for logic cells can be performed without invading the wiring area, and a semiconductor integrated circuit is also disclosed. In the power supply wiring method, a power supply is fed to logic cells located between the functional blocks of a semiconductor integrated circuit comprising a plurality of functional blocks. In the method, power supply provision similar to that for logic cells in the functional blocks is performed for the logic cells between the functional blocks by aligning logic cell rows in the functional blocks and logic cell rows located between the functional blocks. Thus, power supply provision similar to a power supply feeding method for the logic cells in the functional blocks is also possible for the logic cells located between the functional blocks.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: August 15, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kazuhiko Fujimoto
  • Patent number: 6764243
    Abstract: A protruding part formed on one split end part of a boot is temporarily fixed to a recessed part formed on the other split end part in the state where step-shaped hook portions formed on one-end thereof are engagingly locked to each other, and connected by welding, fusion or adhesion. The protruding part is hooked only in one thickness directional side. An overlapping protruding part formed on the non-hook side (inner side) of the recessed part is connected extending over the inside surface of the protruding part and the inside surface of the split end part continued thereto.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: July 20, 2004
    Assignee: NOK Corporation
    Inventors: Yasuaki Inuzuka, Yoshifumi Kojima, Hiromitsu Yamoto, Yukihisa Tateishi, Kenichi Fujimoto, Kazuhiko Fujimoto, Atsushi Nagashima
  • Publication number: 20040060030
    Abstract: A power supply wiring method for a semiconductor integrated circuit is disclosed in which power supply provision for logic cells can be performed without invading the wiring area, and a semiconductor integrated circuit is also disclosed. In the power supply wiring method, a power supply is fed to logic cells located between the functional blocks of a semiconductor integrated circuit comprising a plurality of functional blocks. In the method, power supply provision similar to that for logic cells in the functional blocks is performed for the logic cells between the functional blocks by aligning logic cell rows in the functional blocks and logic cell rows located between the functional blocks. Thus, power supply provision similar to a power supply feeding method for the logic cells in the functional blocks is also possible for the logic cells located between the functional blocks.
    Type: Application
    Filed: September 4, 2003
    Publication date: March 25, 2004
    Inventor: Kazuhiko Fujimoto
  • Patent number: 6216018
    Abstract: A telephone hand-free apparatus comprises a housing; a telephone receiving case installed in the housing, the telephone receiving case being so sized and constructed as to receive therein a portable telephone; a board on which a control circuit is arranged, the board being installed in the housing; an external microphone operatively connected to the control circuit and exposed to the outside of the housing; an external speaker operatively connected to the control circuit and installed in the housing; a connection cable extending from the control circuit, so that when the connection cable is connected to a socket of the portable telephone, the external microphone and the external speaker become operative in place of a microphone and a speaker of the portable telephone; and an electric power source which energizes the control circuit.
    Type: Grant
    Filed: August 5, 1998
    Date of Patent: April 10, 2001
    Assignee: Calsonic Kansei Corporation
    Inventors: Yukio Nakanishi, Yasuhisa Nakahara, Yasuhiro Kobayashi, Yoshihisa Takemori, Koichiro Haga, Kohei Hashimoto, Kazuhiko Fujimoto
  • Patent number: 6128987
    Abstract: A hydraulic press has closed loop feedback control on a slide, a slide pad and bolster cylinders. Hydraulic cylinders actuating various components of the press are controlled according to ideal position estimates to produce consistent and precise pressing action. A closed loop control consists of an ideal position/pressure value generator, a position/pressure detector and an arithmetic unit comparing the ideal and actual position/pressure values. Using the ideal and actual comparison result, the arithmetic unit produces a control signal to drive a cylinder to a desired position/pressure. The hydraulic press is capable of performing several operations on a workpiece in one press cycle, an improvement over presses requiring several operation steps or die changes. The bolster cylinders augment clamping force, reduce shock, and improve die alignment to produce better results with less wear on press components.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: October 10, 2000
    Assignee: Aida Engineering Co., Ltd.
    Inventors: Tatsuji Nakagawa, Itaru Fujimura, Hiroshi Hosoya, Junkichi Comikawa, Kazuhiko Fujimoto