Patents by Inventor Kazuhiko Hatae
Kazuhiko Hatae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10931485Abstract: An adaptive equalization circuit includes: a first filter configure to perform filtering on an input signal based on a tap coefficient; an applying circuit configured to apply, to the signal, noise outside a band of the signal; and a controller configured to set, for the first filter, the tap coefficient that compensates for transmission line characteristics of the signal, based on the signal to which the noise is applied by the applying circuit.Type: GrantFiled: January 3, 2020Date of Patent: February 23, 2021Assignee: FUJITSU LIMITEDInventors: Yuya Imoto, Kazuhiko Hatae, Nobukazu Koizumi, Yasuo Ohtomo, Masashi Sato, Daisuke Sasaki
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Publication number: 20200267030Abstract: An adaptive equalization circuit includes: a first filter configure to perform filtering on an input signal based on a tap coefficient; an applying circuit configured to apply, to the signal, noise outside a band of the signal; and a controller configured to set, for the first filter, the tap coefficient that compensates for transmission line characteristics of the signal, based on the signal to which the noise is applied by the applying circuit.Type: ApplicationFiled: January 3, 2020Publication date: August 20, 2020Applicant: FUJITSU LIMITEDInventors: Yuya IMOTO, KAZUHIKO HATAE, Nobukazu KOIZUMI, Yasuo OHTOMO, Masashi Sato, Daisuke SASAKI
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Patent number: 10560199Abstract: A signal processing circuit includes: a processor configured to adjust phases of reception samples which is supplied at a supply interval, according to a phase adjustment amount; and a processing circuit including a finite impulse response (FIR) filter with taps and configured to process, by the FIR filter, each of the reception samples and output output symbols at an output interval different from the supply interval, the processor is configured to: derive initial values of tap coefficients for the respective taps; and derive the phase adjustment amount such that a center of centroids of the tap coefficients at respective output time points of the output symbols coincides with a center of a number of taps of the FIR filter, the tap coefficients at respective output time points of the output symbols being set according to a deviation between the supply interval and the output interval and the initial values.Type: GrantFiled: January 24, 2019Date of Patent: February 11, 2020Assignee: FUJITSU LIMITEDInventors: Yuya Imoto, Kazuhiko Hatae, Nobukazu Koizumi, Yasuo Ohtomo, Masato Oota, Masashi Sato, Daisuke Sasaki
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Publication number: 20190280779Abstract: A signal processing circuit includes: a processor configured to adjust phases of reception samples which is supplied at a supply interval, according to a phase adjustment amount; and a processing circuit including a finite impulse response (FIR) filter with taps and configured to process, by the FIR filter, each of the reception samples and output output symbols at an output interval different from the supply interval, the processor is configured to: derive initial values of tap coefficients for the respective taps; and derive the phase adjustment amount such that a center of centroids of the tap coefficients at respective output time points of the output symbols coincides with a center of a number of taps of the FIR filter, the tap coefficients at respective output time points of the output symbols being set according to a deviation between the supply interval and the output interval and the initial values.Type: ApplicationFiled: January 24, 2019Publication date: September 12, 2019Applicant: FUJITSU LIMITEDInventors: Yuya IMOTO, KAZUHIKO HATAE, Nobukazu KOIZUMI, Yasuo OHTOMO, Masato OOTA, Masashi Sato, Daisuke SASAKI
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Patent number: 10177855Abstract: An amplitude adjustment circuit includes a memory that stores correspondence information between frequency distributions of an amplitude and adjustment coefficients, a processor configured to generate a frequency distribution of amplitude of data for which adaptive equalization processing has been executed, acquire the correspondence information between frequency distributions of the amplitude and adjustment coefficients from the memory, select the adjustment coefficient based on a result of comparison between the frequency distributions included in the correspondence information acquired by the acquiring unit and the frequency distribution generated by the generating unit, and adjust a gain of the data based on the adjustment coefficient selected by the selecting unit.Type: GrantFiled: October 6, 2017Date of Patent: January 8, 2019Assignee: FUJITSU LIMITEDInventors: Masashi Sato, Kazuhiko Hatae, Nobukazu Koizumi, Yasuo Ohtomo, Masato Oota, Daisuke Sasaki, Yuya Imoto
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Publication number: 20180123701Abstract: An amplitude adjustment circuit includes a memory that stores correspondence information between frequency distributions of an amplitude and adjustment coefficients, a processor configured to generate a frequency distribution of amplitude of data for which adaptive equalization processing has been executed, acquire the correspondence information between frequency distributions of the amplitude and adjustment coefficients from the memory, select the adjustment coefficient based on a result of comparison between the frequency distributions included in the correspondence information acquired by the acquiring unit and the frequency distribution generated by the generating unit, and adjust a gain of the data based on the adjustment coefficient selected by the selecting unit.Type: ApplicationFiled: October 6, 2017Publication date: May 3, 2018Applicant: FUJITSU LIMITEDInventors: Masashi Sato, KAZUHIKO HATAE, Nobukazu KOIZUMI, Yasuo OHTOMO, Masato OOTA, Daisuke SASAKI, Yuya IMOTO
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Patent number: 9680667Abstract: A circuit includes a calculation circuit configured to calculate a noise power of a predetermined-training-sequence pattern repeatedly included in a first signal input into an adaptive equalizer, based on a second signal obtained by compensating the first signal by a compensation circuit, a channel-estimation value based on the second signal, and the predetermined-training-sequence pattern; and an average circuit configured to obtain an average value of estimation values of frequency offsets based on the predetermined-training-sequence pattern having the noise power equal to or smaller than a predetermined power, among estimation values of frequency offsets based on the predetermined-training-sequence pattern, wherein the compensation circuit is configured to compensate a frequency offset of the predetermined-training sequence pattern based on the average value and thereby obtain the second signal, and the adaptive equalizer is configured to perform adaptive-equalization processing of the first signal with aType: GrantFiled: July 6, 2016Date of Patent: June 13, 2017Assignee: FUJITSU LIMITEDInventors: Daisuke Sasaki, Kazuhiko Hatae, Tomoki Katou, Nobukazu Koizumi, Masato Oota, Yasuo Ohtomo, Manabu Yamazaki, Masashi Sato
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Patent number: 9660733Abstract: A signal processing apparatus includes: a filter; and a filter control circuit, wherein the filter control circuit is configured to: detect a power of signals output from the filter; determine one of a plurality of numerical ranges to which the power belongs; update a filter coefficient of the filter according to a determination result; count a number of the signals having the power of a first value or more; set an invalid area which becomes a target not to be determined for each of one or more boundaries between the plurality of numerical ranges when the number of the signals becomes a second value or more; and control a width of the invalid area based on the number of signals.Type: GrantFiled: September 1, 2015Date of Patent: May 23, 2017Assignee: FUJITSU LIMITEDInventors: Masashi Sato, Kazuhiko Hatae, Tomoki Katou, Nobukazu Koizumi, Masato Oota, Yasuo Ohtomo, Manabu Yamazaki, Daisuke Sasaki
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Publication number: 20170012803Abstract: A circuit includes a calculation circuit configured to calculate a noise power of a predetermined-training-sequence pattern repeatedly included in a first signal input into an adaptive equalizer, based on a second signal obtained by compensating the first signal by a compensation circuit, a channel-estimation value based on the second signal, and the predetermined-training-sequence pattern; and an average circuit configured to obtain an average value of estimation values of frequency offsets based on the predetermined-training-sequence pattern having the noise power equal to or smaller than a predetermined power, among estimation values of frequency offsets based on the predetermined-training-sequence pattern, wherein the compensation circuit is configured to compensate a frequency offset of the predetermined-training sequence pattern based on the average value and thereby obtain the second signal, and the adaptive equalizer is configured to perform adaptive-equalization processing of the first signal with aType: ApplicationFiled: July 6, 2016Publication date: January 12, 2017Applicant: FUJITSU LIMITEDInventors: Daisuke SASAKI, KAZUHIKO HATAE, TOMOKI KATOU, Nobukazu KOIZUMI, Masato OOTA, Yasuo OHTOMO, MANABU YAMAZAKI, Masashi Sato
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Patent number: 9496966Abstract: A receiving device that converts, to a digital signal, a signal in which signal light from an optical transmission path and local oscillation light are mixed, so as to perform digital signal processing, the optical communication receiving device comprising: a frequency offset compensation unit configured to calculate a frequency offset of the digital signal and to, based on the frequency offset, compensate for a phase of the digital signal; a carrier phase recovery unit configured to calculate a carrier phase of the digital signal whose phase is compensated for in the frequency offset compensation unit; and a residual frequency offset detection unit configured to calculate an average of differences in the carrier phase, and to output the average as a residual frequency offset, wherein the frequency offset compensation unit is configured to correct the frequency offset using the residual frequency offset output by the residual frequency offset detection unit.Type: GrantFiled: September 24, 2014Date of Patent: November 15, 2016Assignee: FUJITSU LIMITEDInventors: Kazuhiko Hatae, Nobukazu Koizumi, Koji Nakamuta, Manabu Yamazaki, Tomoki Katou, Masashi Sato, Hisao Nakashima
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Patent number: 9401765Abstract: A frequency offset estimation circuit estimates a frequency offset that indicates a difference between a carrier frequency of a received optical signal and a frequency of a local oscillation light used to recover a transmission signal from the received optical signal. The frequency offset estimation circuit includes: a phase difference detector configured to detect a phase difference due to the frequency offset between a first symbol and a second symbol that is transmitted after the first symbol by a specified symbol interval based on a phase of the first symbol and a phase of the second symbol; an estimator configured to estimate the frequency offset based on the phase difference detected by the phase difference detector; and a symbol interval controller configured to specify the symbol interval based on the frequency offset estimated by the estimator.Type: GrantFiled: October 13, 2014Date of Patent: July 26, 2016Assignee: FUJITSU LIMITEDInventors: Nobuaki Kawasoe, Manabu Yamazaki, Kazuhiko Hatae
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Patent number: 9374170Abstract: An optical receiving device includes: an adaptive equalizer that includes a position estimation unit configured to estimate, based on a first signal component and a second signal component of a reception signal generated by reception of a training sequence pattern transmitted from an optical transmitter, a symbol position of the reception signal, and generates an estimated symbol position, a delay unit configured to provide a delay difference between the first signal component and the second signal component, a control unit configured to set a plurality of symbol displacement amount candidates of displacement amounts for the estimated symbol position, causes the delay unit to generate a plurality of delay differences, and generates a channel estimation symbol position used for channel estimation, and an error rate calculation unit configured to calculate an error rate of the signal restored by an adaptive equalization unit.Type: GrantFiled: December 4, 2014Date of Patent: June 21, 2016Assignee: FUJITSU LIMITEDInventors: Masato Oota, Tomoki Katou, Kazuhiko Hatae, Hisao Nakashima, Manabu Yamazaki
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Publication number: 20160134261Abstract: A signal processing apparatus includes: a filter; and a filter control circuit, wherein the filter control circuit is configured to: detect a power of signals output from the filter; determine one of a plurality of numerical ranges to which the power belongs; update a filter coefficient of the filter according to a determination result; count a number of the signals having the power of a first value or more; set an invalid area which becomes a target not to be determined for each of one or more boundaries between the plurality of numerical ranges when the number of the signals becomes a second value or more; and control a width of the invalid area based on the number of signals.Type: ApplicationFiled: September 1, 2015Publication date: May 12, 2016Inventors: Masashi Sato, KAZUHIKO HATAE, TOMOKI KATOU, Nobukazu KOIZUMI, Masato OOTA, Yasuo OHTOMO, MANABU YAMAZAKI, Daisuke SASAKI
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Publication number: 20150180586Abstract: An optical receiving device includes: an adaptive equalizer that includes a position estimation unit configured to estimate, based on a first signal component and a second signal component of a reception signal generated by reception of a training sequence pattern transmitted from an optical transmitter, a symbol position of the reception signal, and generates an estimated symbol position, a delay unit configured to provide a delay difference between the first signal component and the second signal component, a control unit configured to set a plurality of symbol displacement amount candidates of displacement amounts for the estimated symbol position, causes the delay unit to generate a plurality of delay differences, and generates a channel estimation symbol position used for channel estimation, and an error rate calculation unit configured to calculate an error rate of the signal restored by an adaptive equalization unit.Type: ApplicationFiled: December 4, 2014Publication date: June 25, 2015Inventors: Masato OOTA, Tomoki KATOU, Kazuhiko HATAE, Hisao NAKASHIMA, Manabu YAMAZAKI
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Publication number: 20150147071Abstract: A frequency offset estimation circuit estimates a frequency offset that indicates a difference between a carrier frequency of a received optical signal and a frequency of a local oscillation light used to recover a transmission signal from the received optical signal. The frequency offset estimation circuit includes: a phase difference detector configured to detect a phase difference due to the frequency offset between a first symbol and a second symbol that is transmitted after the first symbol by a specified symbol interval based on a phase of the first symbol and a phase of the second symbol; an estimator configured to estimate the frequency offset based on the phase difference detected by the phase difference detector; and a symbol interval controller configured to specify the symbol interval based on the frequency offset estimated by the estimator.Type: ApplicationFiled: October 13, 2014Publication date: May 28, 2015Inventors: Nobuaki Kawasoe, MANABU YAMAZAKI, KAZUHIKO HATAE
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Publication number: 20150098714Abstract: A receiving device that converts, to a digital signal, a signal in which signal light from an optical transmission path and local oscillation light are mixed, so as to perform digital signal processing, the optical communication receiving device comprising: a frequency offset compensation unit configured to calculate a frequency offset of the digital signal and to, based on the frequency offset, compensate for a phase of the digital signal; a carrier phase recovery unit configured to calculate a carrier phase of the digital signal whose phase is compensated for in the frequency offset compensation unit; and a residual frequency offset detection unit configured to calculate an average of differences in the carrier phase, and to output the average as a residual frequency offset, wherein the frequency offset compensation unit is configured to correct the frequency offset using the residual frequency offset output by the residual frequency offset detection unit.Type: ApplicationFiled: September 24, 2014Publication date: April 9, 2015Applicant: Fujitsu LimitedInventors: Kazuhiko HATAE, Nobukazu KOIZUMI, Koji NAKAMUTA, Manabu YAMAZAKI, Tomoki KATOU, Masashi SATO, Hisao NAKASHIMA
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Patent number: 8693898Abstract: An adaptive equalizer includes a finite impulse response filter with a predetermined number of taps; and a tap coefficient adaptive controller having a register to hold tap coefficients for the filter, a weighted center calculator to calculate a weighted center of the tap coefficients, and a tap coefficient shifter to shift the tap coefficients based on a calculation result of the weighted center. During an initial training period, the tap coefficient shifter shifts the tap coefficients on a symbol data basis such that a difference between the calculated weighted center of the tap coefficients and a tap center defined by the number of taps is minimized.Type: GrantFiled: October 14, 2011Date of Patent: April 8, 2014Assignee: Fujitsu LimitedInventors: Nobukazu Koizumi, Kazuhiko Hatae, Noriyasu Nakayama, Koji Nakamuta, Hisao Nakashima, Kosuke Komaki
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Patent number: 8677296Abstract: A computer-readable recording medium stores a design support program that causes a computer to execute a process that includes generating based on a control flow graph conversion result for operation description information concerning a circuit-under-design, a first synthesis result according to which a time length of 1 clock cycle of the circuit-under-design is greater than or equal to a clock period in which the circuit-under-design operates; calculating based on the generated first synthesis result, first circuit scale information indicating a circuit scale of the circuit-under-design; acquiring a second synthesis result that is for the circuit-under-design and conforms to a timing constraint that is based on the control flow graph conversion result; calculating second circuit scale information indicating the circuit scale of the circuit-under-design, based on the generated second synthesis result; and outputting the calculated first circuit scale information and the calculated second circuit information.Type: GrantFiled: January 4, 2013Date of Patent: March 18, 2014Assignee: Fujitsu LimitedInventor: Kazuhiko Hatae
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Patent number: 8606118Abstract: An ALC processing unit to adjust the signal level of outputs from an adaptive equalizer to a target value is provided in a stage later than the adaptive equalizer and earlier than a frequency offset estimation/compensation unit in an optical digital coherent receiver. The ALC processing unit generates a histogram that counts the number of samples for discrete monitored values corresponding to amplitude values of outputs from the adaptive equalizer, and determines a level adjustment coefficient that is to be multiplied by an output from the adaptive equalizer so as to multiply the determined coefficient by the output from the adaptive equalizer so that the monitored value of the peak value of the histogram is the target value.Type: GrantFiled: August 3, 2011Date of Patent: December 10, 2013Assignee: Fujitsu LimitedInventors: Kazuhiko Hatae, Noriyasu Nakayama, Nobukazu Koizumi, Yuji Obana
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Publication number: 20130317802Abstract: An event-driven simulation is performed on an operation of data transmission from a source hardware element to a destination hardware element. Upon receiving a first request for transmitting first data at a first time-point, data stored in a storage area of the destination hardware element is saved as backup data in a memory, and the first data is stored in the storage area. A first time-period for transmitting the first data is measured from the first time-point. When a second request having a higher priority than the first request is received at a second time-point, a portion of the backup data is restored to the storage area so that the storage area stores third data estimated to have been transmitted to the destination hardware element. After a second time-period for the second request is measured, the first data is again stored in the storage area.Type: ApplicationFiled: May 21, 2013Publication date: November 28, 2013Applicant: FUJITSU LIMITEDInventors: Manabu YAMAZAKI, Noriyasu NAKAYAMA, Koji MIGITA, Kazuhiko HATAE, Naoto SHIMOJI, Yasuo OHTOMO