Patents by Inventor Kazuhiko Ishibe
Kazuhiko Ishibe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8433740Abstract: An M-sequence generator includes EXCLUSIVE-OR gates feeding back pieces of bit data from m number of series registers to the registers in response to a clock. A period of a cyclic group {(?1k), (?2k), (?3k), . . . } falls within a maximum period (2m?1), the group being produced as an element (?k) obtained by raising a root ? of a polynomial to a specified power value k (k?2), which have the terms in polynomials of a Galois field GF(2m). In a multiplying unit including the gates, pieces of bit data is fed into one end of the multiplying unit in response to the clock while the element (?k) is fed into the other end. The multiplying unit performs Galois field multiplication between each piece of bit data and the element (?k), the gate supplies the multiplication result as feedback bit data to the respective registers.Type: GrantFiled: April 28, 2010Date of Patent: April 30, 2013Assignee: Anritsu CorporationInventors: Takashi Furuya, Masahiro Kuroda, Kazuhiko Ishibe
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Patent number: 7987395Abstract: A degree of conformity of error distribution of a digital signal to the Poisson distribution is quantitatively determined. The digital signal including error data, which is randomly generated at a predetermined error rate, is divided into data number of measurement units, wherein the data number is determined on the basis of the error rate. A sample number of the measurement units are acquired from the measurement units, and the number of errors contained in each measurement unit is measured as a measurement value. Further, the number of times of occurrence of each measurement value is calculated, a Poisson distribution function is calculated, and a degree of a bond between the Poisson distribution and the distribution of the number of times of occurrence is determined by using the chi-square goodness-of-fit test method.Type: GrantFiled: July 13, 2009Date of Patent: July 26, 2011Assignee: Anritsu CorporationInventors: Masahiro Kuroda, Takashi Furuya, Kazuhiko Ishibe
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Publication number: 20100205235Abstract: An M-sequence generator includes EXCLUSIVE-OR gates feeding back pieces of bit data from m number of series registers to the registers in response to a clock. A period of a cyclic group {(?1k), (?2k), (?3k), . . . } falls within a maximum period (2m-1), the group being produced as an element (?k) obtained by raising a root ? of a polynomial to a specified power value k (k?2), which have the terms in polynomials of a Galois field GF(2m). In a multiplying unit including the gates, pieces of bit data is fed into one end of the multiplying unit in response to the clock while the element (?k) is fed into the other end. The multiplying unit performs Galois field multiplication between each piece of bit data and the element (?k), the gate supplies the multiplication result as feedback bit data to the respective registers.Type: ApplicationFiled: April 28, 2010Publication date: August 12, 2010Applicant: ANRITSU CORPORATIONInventors: Takashi Furuya, Masahiro Kuroda, Kazuhiko Ishibe
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Publication number: 20090282299Abstract: A degree of conformity of error distribution of a digital signal to the Poisson distribution is quantitatively determined. The digital signal including error data, which is randomly generated at a predetermined error rate, is divided into data number of measurement units, wherein the data number is determined on the basis of the error rate. A sample number of the measurement units are acquired from the measurement units, and the number of errors contained in each measurement unit is measured as a measurement value. Further, the number of times of occurrence of each measurement value is calculated, a Poisson distribution function is calculated, and a degree of a bond between the Poisson distribution and the distribution of the number of times of occurrence is determined by using the chi-square goodness-of-fit test method.Type: ApplicationFiled: July 13, 2009Publication date: November 12, 2009Applicant: Anritsu CorporationInventors: Masahiro KURODA, Takashi FURUYA, Kazuhiko ISHIBE
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Patent number: 7450633Abstract: A wander generator has a random number signal generator unit, a filter unit, a clock generator unit, a modulator unit, and a setting unit. The random number generator unit sequentially generates random number signals comprised of a plurality of bits at a constant speed in accordance with a predetermined algorithm. The filter unit receives a random number signal sequence generated by the random number signal generator unit for filtering. The clock generator unit generates a clock signal. The modulator unit modulates the frequency of clock signal generated by the clock generator unit with a signal output from the filter unit. The setting unit applies the filter unit with a signal for setting each amplitude value of a spectrum of a signal sequence output from the filter unit.Type: GrantFiled: March 7, 2007Date of Patent: November 11, 2008Assignee: Anritsu CorporationInventors: Masaharu Uchino, Kazuhiko Ishibe, Takashi Aoki, Ken Mochizuki
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Publication number: 20070286322Abstract: A wander generator has a random number signal generator unit, a filter unit, a clock generator unit, a modulator unit, and a setting unit. The random number generator unit sequentially generates random number signals comprised of a plurality of bits at a constant speed in accordance with a predetermined algorithm. The filter unit receives a random number signal sequence generated by the random number signal generator unit for filtering. The clock generator unit generates a clock signal. The modulator unit modulates the frequency of clock signal generated by the clock generator unit with a signal output from the filter unit. The setting unit applies the filter unit with a signal for setting each amplitude value of a spectrum of a signal sequence output from the filter unit.Type: ApplicationFiled: March 7, 2007Publication date: December 13, 2007Applicant: Anritsu CorporationInventors: Masaharu Uchino, Kazuhiko Ishibe, Takashi Aoki, Ken Mochizuki
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Patent number: 7010444Abstract: A clock generating unit generates a clock signal having a predetermined frequency. A pattern generating unit outputs a data signal having a predetermined pattern in which one frame is configured from a predetermined bit length, so as to be synchronized with the clock signal. A waveform information acquiring unit receives the data signal as a data signal to be measured, and receives the clock signal, and acquires information of waveform in the same time domain of the data signal to be measured and the clock signal. An averaging processing unit carries out averaging processing on an acquired waveform. A phase difference detecting unit detects a phase difference of the data signal to be measured and the clock signal, for each bit, based on an averaged waveform information. A frequency band limiting processing unit carries out predetermined frequency band limiting processing on the per-bit phase difference information.Type: GrantFiled: December 15, 2003Date of Patent: March 7, 2006Assignee: Anritsu CorporationInventors: Tadanori Nishikobara, Kazuhiko Ishibe
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Patent number: 6854068Abstract: In a file, the TDEV mask data information including the TDEV mask data constituted by connecting a plurality of line segments and a calculation expression for forming the TDEV mask data, are stored in advance. A readout section reads out a predetermined TDEV mask data information from the file. A display section displays the line segment which is represented by the desired TDEV mask data information. An operating section inputs information for changing at least one of the start point and the characteristic value to the desired value with respect to the line segment to be represented by the desired TDEV mask data information. A TDEV mask data change section receives information inputted by the operating section and changes TDEV mask data ifnromation based on the calculation expression of the TDEV mask data information, and allows the display section to display the line segment represented by the changed TDEV mask data information.Type: GrantFiled: June 14, 2001Date of Patent: February 8, 2005Assignee: Anritsu CorporationInventors: Kazuhiko Ishibe, Tetsuya Tada
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Publication number: 20040143406Abstract: A clock generating unit generates a clock signal having a predetermined frequency. A pattern generating unit outputs a data signal having a predetermined pattern in which one frame is configured from a predetermined bit length, so as to be synchronized with the clock signal. A waveform information acquiring unit receives the data signal as a data signal to be measured, and receives the clock signal, and acquires information of waveform in the same time domain of the data signal to be measured and the clock signal. An averaging processing unit carries out averaging processing on an acquired waveform. A phase difference detecting unit detects a phase difference of the data signal to be measured and the clock signal, for each bit, based on an averaged waveform information. A frequency band limiting processing unit carries out predetermined frequency band limiting processing on the per-bit phase difference information.Type: ApplicationFiled: December 15, 2003Publication date: July 22, 2004Applicant: Anritsu CorporationInventors: Tadanori Nishikobara, Kazuhiko Ishibe
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Patent number: 6681235Abstract: An amplitude data generator receives L-bit data, and outputs amplitude data of a predetermined periodic function of a phase specified by the data. A frequency setter sets frequency data of (K+L−1) bits obtained by dividing a desired output frequency by a frequency of a predetermined clock signal. A K bit counter counts the clock signal. L-set product and sum computation circuits subject the frequency data of (K+L−1) bits into L-set K-bit data in which a start bit is shifted by one bit each other. Then, these circuits compute a logical product between the counter output of K bits from the counter and a bit unit, and obtains a total number of bits for each set when the computation result is 1. A shifting/adding circuit adds each total number data obtained by the L-set product and sum computation circuits by shifting a bit, and outputs the least significant L bits of the computation result to the amplitude data generator.Type: GrantFiled: February 6, 2001Date of Patent: January 20, 2004Assignee: Anritsu CorporationInventors: Masaharu Uchino, Kazuhiko Ishibe
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Publication number: 20030063662Abstract: A wander generator has a random number signal generator unit, a filter unit, a clock generator unit, a modulator unit, and a setting unit. The random number generator unit sequentially generates random number signals comprised of a plurality of bits at a constant speed in accordance with a predetermined algorithm. The filter unit receives a random number signal sequence generated by the random number signal generator unit for filtering. The clock generator unit generates a clock signal. The modulator unit modulates the frequency of clock signal generated by the clock generator unit with a signal output from the filter unit. The setting unit applies the filter unit with a signal for setting each amplitude value of a spectrum of a signal sequence output from the filter unit.Type: ApplicationFiled: July 25, 2001Publication date: April 3, 2003Applicant: Anritsu CorporationInventors: Masaharu Uchino, Kazuhiko Ishibe, Takashi Aoki
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Publication number: 20020007466Abstract: In a file, the TDEV mask data information including the TDEV mask data constituted by connecting a plurality of line segments and a calculation expression for forming the TDEV mask data, are stored in advance. A readout section reads out a predetermined TDEV mask data information from the file. A display section displays the line segment which is represented by the desired TDEV mask data information. An operating section inputs information for changing at least one of the start point and the characteristic value to the desired value with respect to the line segment to be represented by the desired TDEV mask data information. A TDEV mask data change section receives information inputted by the operating section and changes TDEV mask data ifnromation based on the calculation expression of the TDEV mask data information, and allows the display section to display the line segment represented by the changed TDEV mask data information.Type: ApplicationFiled: June 14, 2001Publication date: January 17, 2002Applicant: Anritsu CorporationInventors: Kazuhiko Ishibe, Tetsuya Tada
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Publication number: 20010016863Abstract: An amplitude data generator receives L-bit data, and outputs amplitude data of a predetermined periodic function of a phase specified by the data. A frequency setter sets frequency data of (K+L−1) bits obtained by dividing a desired output frequency by a frequency of a predetermined clock signal. A K bit counter counts the clock signal. L-set product and sum computation circuits subject the frequency data of (K+L−1) bits into L-set K-bit data in which a start bit is shifted by one bit each other. Then, these circuits compute a logical product between the counter output of K bits from the counter and a bit unit, and obtains a total number of bits for each set when the computation result is 1. A shifting/adding circuit adds each total number data obtained by the L-set product and sum computation circuits by shifting a bit, and outputs the least significant L bits of the computation result to the amplitude data generator.Type: ApplicationFiled: February 6, 2001Publication date: August 23, 2001Applicant: Anritsu CorporationInventors: Masaharu Uchino, Kazuhiko Ishibe
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Patent number: 5563921Abstract: A target signal input to a mixer circuit of a frequency converter is frequency-converted to have a low frequency by a signal obtained by frequency-multiplying an output signal from the voltage-controlled crystal oscillator by M. The frequency-converted output is compared with the output signal from the voltage-controlled crystal oscillator by a phase/frequency comparator. A loop filter receives an error signal based on the phase/frequency comparison and performs loop control to lock the phase of the output signal from the voltage-controlled crystal oscillator to the phase of the output signal from the frequency converter. The jitter component of the target signal exhibiting phase variations at a frequency higher than a loop band contained in the error signal is output from a jitter detection filter before the loop filter via a branching circuit. Even if the target signal having a high frequency undergoes a great frequency change, stable, accurate jitter measurements can be performed following the change.Type: GrantFiled: June 14, 1995Date of Patent: October 8, 1996Assignee: Anritsu CorporationInventors: Etsuji Mesuda, Kazuhiko Ishibe