Abstract: An antenna device of the present embodiment includes: a first conductive layer connected to a ground potential, a semiconductor device provided above the first conductive layer, a second conductive layer provided above the semiconductor device, a first via connecting the second conductive layer and the first conductive layer, a third conductive layer provided above the second conductive layer, a second via passing through the first opening, and an antenna provided above the third conductive layer. A dielectric is provided between the second conductive layer and the semiconductor device, between the third conductive layer and the second conductive layer, and between the antenna and the third conductive layer. The second conductive layer includes a first opening. The second via connects the third conductive layer and the first conductive layer.

Abstract: A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip.

Abstract: A circuit board according to an embodiment is one in which a plurality of electronic components is mounted on a printed wiring board. The circuit board includes a semiconductor component that is mounted on the printed wiring board, and the semiconductor component includes a semiconductor device and a first EBG structure formed on or above the semiconductor device. An operating frequency of the semiconductor device exists outside a cutoff band of the first EBG structure, and the first EBG structure is connected to a ground or a power supply of the printed wiring board.

Abstract: A semiconductor package of an embodiment includes: a semiconductor chip having a signal input terminal and a signal output terminal; and a cap unit that is formed on the semiconductor chip. The cap unit includes a concave portion forming a hollow structure between the semiconductor chip and the cap unit, a first through electrode electrically connected to the signal input terminal, and a second through electrode electrically connected to the signal output terminal. Of the inner side surfaces of the concave portion, a first inner side surface and a second inner side surface facing each other are not parallel to each other.

Abstract: After a TEOS oxide film is formed on the surface of a semiconductor device, a PSG film and an SiN film, which have air permeability, are formed on the surface of the TEOS oxide film. Thereafter, a Poly-Si film is formed thereon. A sacrifice layer is removed by a gaseous HF that passes through the PSG film, the SiN film, and the Poly-Si film, and then, the uppermost layer is covered with a Poly-Si/SiC film. A chip scale package having a thin-film hollow-seal structure can be realized on the semiconductor element.

Abstract: A stimulated phonon emission device of an embodiment is provided with a first electroconductive type of semiconductor substrate of an indirect transition type semiconductor crystal, a second electroconductive type of well region provided in the semiconductor substrate, an element isolation region deeper than the well region, an element region surrounded by the element isolation region, and a field-effect transistor having a plurality of gate electrodes which are formed in the well region in the element region, are parallel to each other, and are arranged at a constant pitch and first electroconductive type of source region and drain region provided in the element regions on the both sides of the gate electrode.

Abstract: A semiconductor device according to an embodiment has: a semiconductor substrate; an acoustic resonator formed on the semiconductor substrate, having a semiconductor layer including impurity electrically isolated from the substrate by depletion layer and configured to resonate at a predetermined resonance frequency based on acoustic standing wave excited in the semiconductor layer; a temperature detector formed on the semiconductor substrate and configured to detect temperature of the semiconductor substrate; a calculating unit formed on the semiconductor substrate and configured to perform calculation of temperature compensation based on the temperature detected by the temperature detector, kind of the impurity and concentration of the impurity; and a controller formed on the semiconductor substrate and configured to control the resonance frequency based on a result of the calculation by the calculating unit.

Abstract: An EBG (Electromagnetic Band Gap) structure according to an embodiment includes: an electrode that is made of a first conductor; a first insulating layer that is provided on the electrode; a patch unit that is provided in substantially parallel with the electrode on the first insulating layer, the patch unit including a first gap, the patch unit being made of a second conductor; a second insulating layer that is provided on the patch unit; a first via that is provided between the patch unit in the first insulating layer and the electrode and connected to the patch unit and the electrode; and a second via that is provided in the first and second insulating layers, the second via piercing the first gap and being connected to the electrode.

Abstract: A semiconductor package according to embodiments includes: a semiconductor chip including a front electrode on a front surface thereof and a back electrode on a back surface thereof; a front-side cap portion including an air gap in a portion between the semiconductor chip and the front-side cap portion and a front-side penetrating electrode, and is positioned to face the front surface of the semiconductor chip; a back-side cap portion bonded with a first cap portion to hermetically seal the semiconductor chip, includes an air gap at least in a portion between the semiconductor chip and the back-side cap portion and a back-side penetrating electrode, and is positioned to face the back surface of the semiconductor chip; a front-side connecting portion which electrically connects the front electrode and the front-side penetrating electrode; and a back-side connecting portion which electrically connects the back electrode and the back-side penetrating electrode.

Abstract: A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip.

Abstract: An EBG structure according to an embodiment includes an electrode unit made of a first conductor and provided with a space, a patch unit provided approximately parallel to the electrode unit and made of a second conductor, an insulating layer provided between the electrode unit and the patch unit, a first via provided between the patch unit and the electrode unit in the insulating layer and connected to the patch unit and the electrode unit, and a second via provided between the patch unit and the space in the insulating layer, connected to the patch unit, and not connected to the electrode unit.

Abstract: A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip.

Abstract: A semiconductor device according to an embodiment includes: a first unit device configured to include a semiconductor chip, a backside electrode that is in contact with a backside of the semiconductor chip, and a bonding wire in which one end is connected to the backside electrode; a second unit device configured to have a function different from that of the first unit device; a resin layer configured to fix the first and second unit devices to each other; and a first wiring that is formed on the resin layer on a surface side of the semiconductor chip and connected to the other end of the bonding wire.

Abstract: An antenna device of the present embodiment includes: a first conductive layer connected to a ground potential, a semiconductor device provided above the first conductive layer, a second conductive layer provided above the semiconductor device, a first via connecting the second conductive layer and the first conductive layer, a third conductive layer provided above the second conductive layer, a second via passing through the first opening, and an antenna provided above the third conductive layer. A dielectric is provided between the second conductive layer and the semiconductor device, between the third conductive layer and the second conductive layer, and between the antenna and the third conductive layer. The second conductive layer includes a first opening. The second via connects the third conductive layer and the first conductive layer.

Abstract: A semiconductor device of an embodiment includes: a substrate, a high-frequency integrated circuit being provided on the substrate, a cap, and a sealing wall provided between the substrate and the cap. The cap includes a first conductive layer, a second conductive layer, an insulating layer provided between the first conductive layer and the second conductive layer, and a conductive via provided in the insulating layer. The conductive via connects the first conductive layer and the second conductive layer. The first conductive layer or the second conductive layer is connected to a ground potential. The sealing wall surrounds the high-frequency integrated circuit.

Abstract: A semiconductor package of an embodiment includes: a semiconductor chip having a signal input terminal and a signal output terminal; and a cap unit that is formed on the semiconductor chip. The cap unit includes a concave portion forming a hollow structure between the semiconductor chip and the cap unit, a first through electrode electrically connected to the signal input terminal, and a second through electrode electrically connected to the signal output terminal. Of the inner side surfaces of the concave portion, a first inner side surface and a second inner side surface facing each other are not parallel to each other.

Abstract: An inkjet recording head of an embodiment includes: an elastic film provided to form a part of a pressure-generating chamber connected to a nozzle opening; and a piezoelectric film-laminated part, an end thereof being fixed to the elastic film, a central part thereof facing the elastic film having an air gap in-between, the piezoelectric film-laminated part including a lower electrode, a piezoelectric film, and an upper electrode.

Abstract: A semiconductor device according to an embodiment includes: a first unit device configured to include a semiconductor chip, a backside electrode that is in contact with a backside of the semiconductor chip, and a bonding wire in which one end is connected to the backside electrode; a second unit device configured to have a function different from that of the first unit device; a resin layer configured to fix the first and second unit devices to each other; and a first wiring that is formed on the resin layer on a surface side of the semiconductor chip and connected to the other end of the bonding wire.

Abstract: After a TEOS oxide film is formed on the surface of a semiconductor device, a PSG film and an SiN film, which have air permeability, are formed on the surface of the TEOS oxide film. Thereafter, a Poly-Si film is formed thereon. A sacrifice layer is removed by a gaseous HF that passes through the PSG film, the SiN film, and the Poly-Si film, and then, the uppermost layer is covered with a Poly-Si/SiC film. A chip scale package having a thin-film hollow-seal structure can be realized on the semiconductor element.

Abstract: A stimulated phonon emission device of an embodiment is provided with a first electroconductive type of semiconductor substrate of an indirect transition type semiconductor crystal, a second electroconductive type of well region provided in the semiconductor substrate, an element isolation region deeper than the well region, an element region surrounded by the element isolation region, and a field-effect transistor having a plurality of gate electrodes which are formed in the well region in the element region, are parallel to each other, and are arranged at a constant pitch and first electroconductive type of source region and drain region provided in the element regions on the both sides of the gate electrode.