Patents by Inventor Kazuhiko Kamimura

Kazuhiko Kamimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240160746
    Abstract: An analysis condition for security risk for a data flow in a system to be analyzed is automatically generated. An analysis condition generating apparatus lA generates from a natural sentence, using ontology in which a relationship is described between one or more nodes on a data flow graph that indicates a data flow in a system to be analyzed and one or more edges that indicate an event related to the nodes, graph structural data indicating the relationship between the nodes and the edges, and generates an analysis condition for analyzing security risk for the system to be analyzed based on the graph structural data.
    Type: Application
    Filed: March 19, 2021
    Publication date: May 16, 2024
    Applicant: NEC Corporation
    Inventors: Junpei KAMIMURA, Kazuhiko Isoyama, Yoshiaki Sakae
  • Publication number: 20240146757
    Abstract: It is determined whether to involve the security risk based on the data flow in the system to be analyzed. An analysis apparatus 1A a historical information collecting unit 220A configured to collect historical information on an operational history for a program executed in a system to be analyzed, an information adding unit 230 configured to add to the historical information, external information obtained from an information resource other than an information processing apparatus that executes the program, and a risk determining unit 180A configured to perform a risk determining processing for determining based on preset determining condition, whether to involve security risk in the historical information to which the external information is added.
    Type: Application
    Filed: March 19, 2021
    Publication date: May 2, 2024
    Applicant: NEC Corporation
    Inventors: Kazuhiko lsoyama, Junpei Kamimura, Yoshiaki Sakae
  • Patent number: 3996497
    Abstract: A protective circuit effective for use with an output capacitor less type transistor amplifier includes a load impedance detecting circuit and a detecting circuit for detecting an undesirable DC voltage applied to a load. The load impedance detecting circuit comprises first and second DC bridge circuits for detecting a load impedance, and the DC voltage detecting circuit comprises third and fourth DC bridge circuits. Both the load and amplifier are protected by outputs from the first through fourth bridge circuits so as to be free from a load-shorted state and an undesirable DC voltage.
    Type: Grant
    Filed: January 27, 1975
    Date of Patent: December 7, 1976
    Assignee: Sony Corporation
    Inventor: Kazuhiko Kamimura
  • Patent number: 3974455
    Abstract: A transistor amplifier comprising a bipolar transistor having an input electrode and a pair of output electrodes, one of the output electrodes being coupled to the gate electrode of a field effect transistor, the field effect transistor having triode-type dynamic characteristics. Respective sources of operating potential are coupled to the bipolar and field effect transistors. To stabilize the DC bias current flowing through the field effect transistor in the event of fluctuations of the operating potential supplied thereto, a portion of such fluctuations is injected into the other output electrode of the bipolar transistor. The field effect transistor is adapted to drive a load impedance.
    Type: Grant
    Filed: May 15, 1975
    Date of Patent: August 10, 1976
    Assignee: Sony Corporation
    Inventors: Kazuhiko Kamimura, Tadao Yoshida
  • Patent number: 3968451
    Abstract: A transistor amplifier comprised of a transistor supplied with a first operating voltage and a field effect transistor having triode-type dynamic characteristics and supplied with a second operating voltage. The gate electrode of the field effect transistor is coupled to the transistor collector. In order to stabilize the field effect transistor bias current in the event of fluctuations in the second operating voltage, a voltage control circuit is responsive to such fluctuations to alter the first operating voltage so as to vary the gate voltage applied to the field effect transistor in a direction to stabilize the bias current.
    Type: Grant
    Filed: May 16, 1975
    Date of Patent: July 6, 1976
    Assignee: Sony Corporation
    Inventors: Kazuhiko Kamimura, Tadao Yoshida
  • Patent number: 3968450
    Abstract: A transistor amplifier comprised of a field effect transistor having triode-type dynamic characteristics in combination with a bipolar transistor. The current flowing through the field effect transistor is a function of an input signal. The bipolar transistor is substantially nonconductive until the field effect transistor current reaches a threshold level and then current flows through the bipolar transistor as a function of the input signal. The currents produced by the field effect and bipolar transistors are supplied to a load.
    Type: Grant
    Filed: March 20, 1975
    Date of Patent: July 6, 1976
    Assignee: Sony Corporation
    Inventors: Tadao Suzuki, Kazuhiko Kamimura