Abstract: An electronic game machine including a central processing unit, a storing device, a display, and an inputting device. The central processing unit serves as a game board displaying unit to display a game board on a display, a game piece deploy controlling unit to initially deploy game pieces, and a game piece movement permitting unit to permit the movement of the game pieces.

Abstract: An electronic game machine including a central processing unit, a storing device, a display, and an inputting device. The central processing unit serves as a game board displaying unit to display a game board on a display, a game piece deploy controlling unit to initially deploy game pieces, and a game piece movement permitting unit to permit the movement of the game pieces.

Abstract: There is provided play equipment which includes a game board 4 in which the number of intersected lines at an intersection point is counted as scores and the obtained score can be understood even in a state where game pieces are deployed and game pieces in two colors on both front and rear sides of each of which a plurality of totally different graphics having the same number is written. The game pieces each having one of the two colors are constructed by combinations of a plurality of solid game pieces 7 and 8 having the same shape whose front and rear can be reversed and of a plurality of hollow game pieces and 12 having the same shape whose front and rear can be reversed and which can be fitted in the solid game pieces 7 and 8 and have space for writing each graphics.

Abstract: A broadcasting system which permits broadcast of high dignity by rationalized equipment is provided. In this broadcasting station, the N-th affiliated station forwards program material data, CM material data and organization information data to a central station via an ATM/LAN, and registration means registers and stores such data into a program bank, a CM bank and a data server. Automatic sending control means and automatic sending means for the N-th affiliated station take out materials from the program bank, the CM bank or a CM bank for different J-th affiliated station, etc. under real time management of time management means on the basis of organization information registered and stored in the data server to organize televising contents to send out the televising contents to the N-th affiliated station via a dedicated digital line.

Abstract: A damping intermediate pillar, which can exhibit a sufficient resistance against the horizontal force of a strong earthquake by reinforcing the joins between the damping intermediate pillar and the upper and lower beams, is disclosed. A damping intermediate pillar 14, used for a building or a structure configured of pillars 1 and beams 3, is divided into upper and lower damping intermediate pillar portions 14a, 14b of H shape steel, and includes a plurality of inner steel plates 7b fixed on the damping intermediate pillar portion 14b and a plurality of outer steel plates 7a fixed on the other damping intermediate pillar portion 14a. The inner and outer steel plates are arranged alternately in a single or a plurality of layers, between which a viscoelastic member 15 is held to make up a viscoelastic damper 17. The coupling end surfaces of the intermediate pillar portions 14a, 14b directed vertically are fixed on the upper and lower floor beams 3a, 3b.

Abstract: A broadcasting system which permits broadcast of high dignity by rationalized equipment is provided. In this broadcasting station, the N-th affiliated station SatN forwards program material data (24a), CM material data (25a) and organization information data (26a) to a central station Cbs via an ATM/LAN (50), and registration means (1) registers and stores such data into a program bank (4), a CM bank (5) and a data server (2). Automatic sending control means (9) and automatic sending means (10) for the N-th affiliated station take out materials from the program bank (4), the CM bank (5) or a CM bank (6) for different J-th affiliated station, etc. under real time management of time management means (15) on the basis of organization information registered and stored in the data server (2) to organize televising contents Oacn to send out the televising contents to the N-th affiliated station SatN via a dedicated digital line (51).

Abstract: A damping intermediate pillar, which can exhibit a sufficient resistance against the horizontal force of a strong earthquake by reinforcing the joins between the damping intermediate pillar and the upper and lower beams, is disclosed. A damping intermediate pillar 14, used for a building or a structure configured of pillars 1 and beams 3, is divided into upper and lower damping intermediate pillar portions 14a, 14b of H shape steel, and includes a plurality of inner steel plates 7b fixed on the damping intermediate pillar portion 14b and a plurality of outer steel plates 7a fixed on the other damping intermediate pillar portion 14a. The inner and outer steel plates are arranged alternately in a single or a plurality of layers, between which a viscoelastic member 15 is held to make up a viscoelastic damper 17. The coupling end surfaces of the intermediate pillar portions 14a, 14b directed vertically are fixed on the upper and lower floor beams 3a, 3b.

Abstract: A supply side converts, into an information fragment, each of a lot of articles and advertisements provided by publishing sources such as a newspaper company and a plurality of advertisement sources, and codes and delivers the information fragments. The supply side makes a subscription contract including a restricted genre and period with a viewer side via a bidirectional communication medium. The supply side supplies a decoding key that is effective only within the confines of the contract and thereby allows the viewer side to capture and display only information fragments that satisfy the contract. The supply side charges the viewer side for only the captured fragments and collects a fee from the viewer side. Further, on-page advertisement fragments or flier fragments are linked to article fragments so that when an article fragment or an advertisement fragment is captured, the other is also captured and displayed.

Abstract: Program production supporting component, transmission equipment controlling component, material creation managing component, and storing component are interconnected through a network, and managing component and exterior supporting component are connected to the network, thereby making it possible to realize a program production and transmission apparatus capable of efficiently execution creation of program component information with production information produced based on production schedule information, creation of a program progress table formed based on the program component information, and processing for editing and transmission based on the program progress table at timing as required.

Abstract: A fitting for effecting a bolted connection between a beam and a column in a steel frame structure includes a beam connecting portion and a column connecting portion. In addition, reinforcing elements are provided to strengthen the bracket and resist vertical eccentricity and loading caused by the particular bolted connection. The various embodiments of the bracket are particularly useful in the context of repairing cracked or damaged weld connections at the beam/column interface in existing steel structures, but have application in the context of upgrading or reinforcing existing weld connections that may not otherwise be damaged. Also, the bracket can be used in new steel frame constructions.

Abstract: An input buffer circuit includes an output circuit and supplies a plurality of signals in response to an input signal. A delay line is constituted of a plurality of delay cells connected in series and delays the signals supplied from the input buffer circuit. A PLL circuit connected to the delay line, includes a level converter which outputs a control signal for controlling a delay time of the delay line. An output signal generation circuit generates a signal having a multiplied frequency from the output signal of the input buffer circuit and the output signal of a tap of the delay line. Each of the delay cells has an output circuit having the same arrangement as that of the output circuit provided in the input buffer circuit, and a clocked inverter circuit included in each of the output circuits of the delay cells and input buffer circuit is controlled by the control signal output from the level converter.

Abstract: A differential current source circuit includes three P-channel MOSFETs and two N-channel MOSFETs. Each source of first and second P-channel MOSFETs is connected to a power supply, and a bias voltage is applied to each gate of the MOSFETs. A current path of the first N-channel MOSFET is connected between a drain of the first P-channel MOSFET and a ground. A current path of the third P-channel MOSFET is connected between a drain of the second P-channel MOSFET and a current output terminal. A gate of the third P-channel MOSFET is connected to the drain of the first P-channel MOSFET. One end of a current path of the second N-channel MOSFET is connected to a connecting point of the first P-channel and first N-channel MOSFETs, and the other end is connected to a connecting point of the second P-channel and third P-channel MOSFETs. A digital signal is applied to a gate of the second N-channel MOSFET.

Abstract: The output terminal of an ECL circuit is directly connected to the input terminal of a CMOS output circuit. The CMOS output circuit has a transistor which sets the threshold voltage of the CMOS output circuit nearly midway between ECL logic levels. A first reference voltage generating circuit has substantially the same arrangement as the CMOS output circuit and outputs a potential midway between CMOS logic levels as a first reference voltage Vref1. The first reference voltage Vref1 is made variable. A second reference voltage generating circuit has substantially the same arrangement as the ECL circuit and outputs a potential which is midway between the ECL logic levels as a second reference voltage Vref2. A comparator makes a comparison between the first and second reference voltages Vref1 and Vref2 and controls the first reference voltage generating circuit and the CMOS output circuit so that the first and second reference voltages Vref1 and Vref2 may become equal to each other.

Abstract: In a sense amplifier circuit, an output potential is set in a data output state when an operation of the sense amplifier is a worst pass before the start of read access. In a memory read mode, when data corresponding to the worst-pass operation of the sense amplifier circuit is read out, the circuit is previously set in a corresponding data output state. A time delay (gate delay) by a gate does not occur. In contrast, when data corresponding to the best-pass operation of the sense amplifier circuit is read out, the gate delay occurs by this operation. The gate delay, however, is shorter than that of the worst pass. As a result, only the best pass is present as the operation mode of the sense amplifier circuit. Therefore, a high operation speed is achieved, so that a high read speed of the entire memory is achieved.

Abstract: The gate of a first P-channel transistor of a first comparator is supplied with an input signal, and the gate of a second P-channel transistor of the first comparator is supplied with a reference voltage. An output terminal of the first comparator is connected to an output circuit and the gates of first and second P-channel transistors of a second comparator are supplied with the reference voltage. The second comparator outputs a voltage equal to a stand-by time output voltage of the first comparator and the output voltage from the second comparator is supplied to the non-inversion input terminal of a third comparator which is connected to a voltage generating circuit. The voltage generating circuit has substantially the same dimension ratio as the output circuit and generates a voltage equal to the threshold voltage of the output circuit.

Abstract: This invention discloses a switching constant current source circuit including a first current path for supplying a constant current, a first MOS transistor, one end of a current path of which is connected to the first current path, the other end of the current path of which is connected to a second current path, and a gate of which is applied with a digital signal corresponding to a logical amplitude, a second MOS transistor, one end of a current path of which is connected to the first current path, the other end of the current path of which is connected to a third current path, and which performs a switching operation complementary with the first MOS transistor, and level conversion means for fetching a change in voltage in the first current path caused by a change in current flowing through the first current path according to an operation of the first MOS transistor in response to the digital signal, and alternately applying a first level for disabling the second MOS transistor, which operates complementar

Abstract: A sense amplifier of this invention has a main characteristic feature in that it has low power consumption in an input waiting state, and can perform a highspeed sensing operation. The sense amplifier includes an output transistor, a constant current source connected between the base of the transistor and a first power source, a MOS transistor, having a source-drain path connected between the base of the transistor and a second power source, for receiving most of a current from the constant current source, and a load resistor for the transistor. The base potential of the output transistor in the input waiting state is set to be a value corresponding to a state immediately before or after the transistor is turned on.

Abstract: A MOS transistor includes a gate electrode layer formed on an insulation layer which is formed on an element formation region defined by a field insulation layer formed on a P-type semiconductor substrate. The gate electrode layer has first and second openings formed therein. Further, N-type impurity diffusion regions acting as the drain and source of the MOS transistor are formed in those portions of the surface area of the semiconductor substrate which lie under the first and second openings.

Abstract: This invention is a D/A converter including a preset current source, first and second differential switches for selectively deriving an output current of the preset current source in response to complementary signals supplied to control electrodes thereof, and an imaginary short circuit for connecting output portions of current paths of the switches to each other. Variation in the voltage at the time of switching operation of the differential switch can be suppressed by use of the imaginary short circuit with the above construction, thus making it possible to enhance the operation speed.

Abstract: A digital-to-analog converter which has an input terminal for receiving first and second digital signals and a reference voltage generating circuit for establishing a reference voltage at a control terminal of a reference voltage transistor. The digital-to-analog converter also includes first and second current sources which each include a current source transistor having a control terminal connected to the control terminal of the voltage reference transistor. A first switch connected in the conduction path of the first current source transistor selectively allows current to flow to the output terminal and a second switch connected in the conduction path of the second current source transistor selectively allows a second current to flow to the output terminal.