Patents by Inventor Kazuhiko Kusuda

Kazuhiko Kusuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device reducing output capacitance due to parasitic capacitance
    Patent number: 7968943
    Abstract: Plural through-holes are formed in a region of a semiconductor substrate positioned below a drain region (an element region other than a P-type well region). According to this configuration, an opposing area of the drain region and the semiconductor substrate can be reduced. Therefore, a drain-substrate capacitance Cdsub is reduced, and an output capacitance Coss of an SOI LDMOSFET can be reduced as a result.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: June 28, 2011
    Assignee: Panasonic Electric Works Co., Ltd.
    Inventors: Takuya Sunada, Kazuhiko Kusuda, Takeshi Yoshida
  • SEMICONDUCTOR DEVICE REDUCING OUTPUT CAPACITANCE DUE TO PARASITIC CAPACITANCE
    Publication number: 20090321827
    Abstract: Plural through-holes are formed in a region of a semiconductor substrate positioned below a drain region (an element region other than a P-type well region). According to this configuration, an opposing area of the drain region and the semiconductor substrate can be reduced. Therefore, a drain-substrate capacitance Cdsub is reduced, and an output capacitance Coss of an SOI LDMOSFET can be reduced as a result.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 31, 2009
    Applicant: PANASONIC ELECTRIC WORKS CO., LTD.
    Inventors: Takuya SUNADA, Kazuhiko KUSUDA, Takeshi YOSHIDA