Patents by Inventor Kazuhiko Muraoka

Kazuhiko Muraoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11962920
    Abstract: An imaging device of the present disclosure includes: a pixel array section in which pixels including light receiving elements are arranged; a first pixel control section that performs control to read out signals of all the pixels in the pixel array section at a first frame rate; a second pixel control section that performs control to read out signals of the pixels in a specific region in the pixel array section at a second frame rate higher than the first frame rate; and an analog-to-digital conversion section that performs an analog-to-digital conversion on a pixel signal read out by the control performed by the first pixel control section or the second pixel control section.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: April 16, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Kazuhiko Muraoka
  • Patent number: 11956559
    Abstract: Imaging devices are disclosed. In one example, an imaging device includes a pixel array with light-receiving pixels that are separated pixel lines, and that accumulating electric charge in an accumulation period. An exposure controller sets time lengths of the accumulation such that the time lengths repeat in predetermined order. The accumulation period includes a first accumulation period and a second accumulation period each having a first time length, and a third accumulation period and a fourth accumulation period each having a second time length. A processor generates image data by adding pixel values based on the accumulation result in a first pixel line in the first accumulation period, the accumulation result in a second pixel line in the second accumulation period, the accumulation result in the first pixel line in the third accumulation period, and the accumulation result in the second pixel line in the fourth accumulation period.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: April 9, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Kazuhiko Muraoka
  • Patent number: 11778342
    Abstract: Image quality is to be improved in a solid-state image pickup element that performs time delay integration. A correlated double sampling circuit generates a frame in which a predetermined number of lines each including a plurality of digital signals are arranged. A TDI frame memory retains a (K?1)-th frame generated before a K-th frame. A time delay integration circuit performs time delay integration processing of adding the line having a predetermined address in the K-th frame and the line having an address at a certain distance from the predetermined address in the (K?1)-th frame.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: October 3, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Tomohiro Yamazaki, Yoshinori Muramatsu, Shigetaka Kudo, Kazuhiko Muraoka
  • Publication number: 20220353441
    Abstract: An imaging device of the present disclosure includes: a pixel array section in which pixels including light receiving elements are arranged; a first pixel control section that performs control to read out signals of all the pixels in the pixel array section at a first frame rate; a second pixel control section that performs control to read out signals of the pixels in a specific region in the pixel array section at a second frame rate higher than the first frame rate; and an analog-to-digital conversion section that performs an analog-to-digital conversion on a pixel signal read out by the control performed by the first pixel control section or the second pixel control section.
    Type: Application
    Filed: June 1, 2020
    Publication date: November 3, 2022
    Inventor: KAZUHIKO MURAOKA
  • Publication number: 20220295000
    Abstract: Image quality is to be improved in a solid-state image pickup element that performs time delay integration. A correlated double sampling circuit generates a frame in which a predetermined number of lines each including a plurality of digital signals are arranged. A TDI frame memory retains a (K?1)-th frame generated before a K-th frame. A time delay integration circuit performs time delay integration processing of adding the line having a predetermined address in the K-th frame and the line having an address at a certain distance from the predetermined address in the (K?1)-th frame.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 15, 2022
    Inventors: Tomohiro Yamazaki, Yoshinori Muramatsu, Shigetaka Kudo, Kazuhiko Muraoka
  • Patent number: 11252348
    Abstract: An imaging device of the present disclosure includes a detection unit that detects a specific region in a taken image as a region of interest, a control unit that performs control to read out a pixel signal at first pixel resolution in a region including the region of interest and read out a pixel signal at second pixel resolution lower than the first pixel resolution in a region not including the region of interest, and an analog-digital conversion unit that converts the pixel signal read out by the control by the control unit into a digital signal.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: February 15, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Kazuhiko Muraoka
  • Publication number: 20210152758
    Abstract: An imaging device of the present disclosure includes a detection unit that detects a specific region in a taken image as a region of interest, a control unit that performs control to read out a pixel signal at first pixel resolution in a region including the region of interest and read out a pixel signal at second pixel resolution lower than the first pixel resolution in a region not including the region of interest, and an analog-digital conversion unit that converts the pixel signal read out by the control by the control unit into a digital signal.
    Type: Application
    Filed: April 19, 2019
    Publication date: May 20, 2021
    Inventor: KAZUHIKO MURAOKA
  • Patent number: 8640178
    Abstract: Distribution of contents through a network with reduced load on a server is enabled. Moreover, distribution with higher security is enabled. A server side connected to a predetermined network has a content database for managing data related to contents that can be distributed, a content cluster list containing data related to division of each content into clusters, and a cluster database related to an address where each cluster is stored. A device side that can be connected to the server saves at least a part of clusters of a received content by each cluster formed by dividing the content, and transfers a predetermined cluster saved by content saving processing to an indicated address in response to a request for transfer of a cluster of the received content.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: January 28, 2014
    Assignee: Sony Corporation
    Inventor: Kazuhiko Muraoka
  • Publication number: 20050034150
    Abstract: Distribution of contents through a network with reduced load on a server is enabled. Moreover, distribution with higher security is enabled. A server side connected to a predetermined network has a content database for managing data related to contents that can be distributed, a content cluster list containing data related to division of each content into clusters, and a cluster database related to an address where each cluster is stored. A device side that can be connected to the server saves at least a part of clusters of a received content by each cluster formed by dividing the content, and transfers a predetermined cluster saved by content saving processing to an indicated address in response to a request for transfer of a cluster of the received content.
    Type: Application
    Filed: July 30, 2004
    Publication date: February 10, 2005
    Applicant: SONY CORPORATION
    Inventor: Kazuhiko Muraoka
  • Patent number: 6651092
    Abstract: A system and method are disclosed for managing an assignment of IP addresses in a cable modem system. According to the disclosed system and method, an IP address of a specific kind is assigned to a client according to the classification of the client. A private IP address is issued in case of the client being a cable modem and a global IP address is issued in other cases so that the number of global addresses needed in the cable modem system can be reduced.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: November 18, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuhiko Muraoka