Patents by Inventor Kazuhiko Ninomiya

Kazuhiko Ninomiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8602890
    Abstract: To provide a game device capable of improving reality regarding an operation of a game in which an attack on one or more attack targets is performed. Remaining number-of-times information storage means (70) stores remaining number-of-times information that indicates a remaining number of times an attack on one or more attack targets can be performed. Display means (74) displays a screen that includes a first image, containing a plurality of reference regions, and a second image. Image moving means (72) moves at least one of the first image and the second image according to a direction instructing operation of a player. Remaining number-of-times information update means (76) increases the remaining number of times the attack on one or more attack target can be performed based on a number of one or more reference regions included in a superposition region in which the first image and the second image are superposed on each other.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: December 10, 2013
    Assignee: Konami Digital Entertainment Co., Ltd.
    Inventors: Mitsuhiro Nomi, Fumiaki Oshita, Kazuto Nishimura, Kazuhiko Ninomiya, Takaharu Ikeda
  • Publication number: 20100261528
    Abstract: To provide a game device capable of improving reality regarding an operation of a game in which an attack on one or more attack targets is performed. Remaining number-of-times information storage means (70) stores remaining number-of-times information that indicates a remaining number of times an attack on one or more attack targets can be performed. Display means (74) displays a screen that includes a first image, containing a plurality of reference regions, and a second image. Image moving means (72) moves at least one of the first image and the second image according to a direction instructing operation of a player. Remaining number-of-times information update means (76) increases the remaining number of times the attack on one or more attack target can be performed based on a number of one or more reference regions included in a superposition region in which the first image and the second image are superposed on each other.
    Type: Application
    Filed: August 11, 2008
    Publication date: October 14, 2010
    Applicant: KONAMI DIGITAL ENTERTAINMENT CO., LTD.
    Inventors: Mitsuhiro Nomi, Fumiaki Oshita, Kazuto Nishimura, Kazuhiko Ninomiya, Takaharu Ikeda
  • Patent number: 7317999
    Abstract: A method for mapping a spectrum obtained from signals under test corresponding to linearly spaced frequencies to logarithmically spaced frequencies in a measuring apparatus. A spectrum within a predetermined frequency range from logarithmically spaced frequencies is selected from this spectrum corresponding to linearly spaced frequencies and vector averaging of the selected spectrum is performed.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: January 8, 2008
    Assignee: Agilent Technologies, Inc.
    Inventors: Kazuhiko Ninomiya, Yoshiyuki Yanagimoto
  • Publication number: 20050240367
    Abstract: A method for mapping a spectrum obtained from signals under test corresponding to linearly spaced frequencies to logarithmically spaced frequencies in a measuring apparatus. A spectrum within a predetermined frequency range from logarithmically spaced frequencies is selected from this spectrum corresponding to linearly spaced frequencies and vector averaging of the selected spectrum is performed.
    Type: Application
    Filed: April 8, 2005
    Publication date: October 27, 2005
    Inventors: Kazuhiko Ninomiya, Yoshiyuki Yanagimoto
  • Patent number: 6145024
    Abstract: An input/output data transfer system capable of integrating input/output data transfer on a plurality of input/output interface cables into data transfer on a single serial input/output interface cable for substantially reducing the number of input/output interface cables required for a host computer system. A multiplexer channel device is provided with a plurality of channels which serve as logical channels corresponding to conventional physical channel paths from a viewpoint of an operating system running on the host computer system. A multiplexer port device is provided with a plurality of input/output ports on a switching device or input/output device, each of these channels and ports shares a large-capacity input/output interface, and a channel path multiplexing function is performed for enabling frame-by-frame multiplexing and simultaneous input/output operations on plural channels.
    Type: Grant
    Filed: June 1, 1998
    Date of Patent: November 7, 2000
    Assignees: Hitachi, Ltd., Hitachi Information Technology Co., Ltd.
    Inventors: Hirofumi Maezawa, Kazuhiko Ninomiya
  • Patent number: 5646541
    Abstract: A circuit network measuring apparatus applies a measurement signal from a signal source to a device under test and measures circuit parameters of the device under test from the measurement signal and an output signal of the device under test. The apparatus includes a function which adds a frequency follow-up algorithm to a computer control portion to vary the output frequency of the signal source, thereby performing control such that the measured value will substantially equal a given value.
    Type: Grant
    Filed: March 22, 1995
    Date of Patent: July 8, 1997
    Assignee: Hewlett-Packard Company
    Inventor: Kazuhiko Ninomiya
  • Patent number: 4788638
    Abstract: An apparatus transfers data between a plurality of input/output (I/O) devices and a main storage unit and includes a plurality of channel devices and a channel control unit. Each channel device is provided with a first data buffer for holding data to be transferred to and transferred from an I/O device. The channel control unit has an address register and a second data buffer. An address register is provided for each channel device, and holds an address of the main storage unit at which address the data to and from the I/O device is stored, and the second data buffer holds the data to be transferred to and transferred from the I/O device, which data is accessed based on the address designated by the address register. A data bus is connected between the first and second data buffers, the data bus having a bit capacity larger than that for data transfer between the I/O device and the channel device.
    Type: Grant
    Filed: December 11, 1986
    Date of Patent: November 29, 1988
    Assignee: Hitachi, Limited
    Inventors: Tetsuji Ogawa, Tadashi Sato, Kazuhiko Ninomiya, Hideaki Shibata, Ryo Yamagatu