Abstract: A radio-frequency power amplifier device includes: a carrier amplifier semiconductor device and a peak amplifier semiconductor device on a multilayer submount substrate; a bias power supply semiconductor device; second radio-frequency signal wiring that transmits a radio-frequency signal to the carrier amplifier semiconductor device and the peak amplifier semiconductor device; and carrier-amplifier bias power supply wiring that is wired in a third wiring layer and supplies a bias power supply voltage. The second radio-frequency signal wiring and the carrier-amplifier bias power supply wiring intersect in a plan view. The radio-frequency power amplifier device includes: a shield pattern that is located in a second wiring layer between a first wiring layer and the third wiring layer; and one or more connection vias disposed in an extension direction of the carrier-amplifier bias power supply wiring. The one or more connection vias are connected to the shield pattern.

Abstract: A radio-frequency power amplifier device includes: a carrier amplifier semiconductor device and a peak amplifier semiconductor device on a multilayer submount substrate; a bias power supply semiconductor device; second radio-frequency signal wiring that transmits a radio-frequency signal to the carrier amplifier semiconductor device and the peak amplifier semiconductor device; and carrier-amplifier bias power supply wiring that is wired in a third wiring layer and supplies a bias power supply voltage. The second radio-frequency signal wiring and the carrier-amplifier bias power supply wiring intersect in a plan view. The radio-frequency power amplifier device includes: a shield pattern that is located in a second wiring layer between a first wiring layer and the third wiring layer; and one or more connection vias disposed in an extension direction of the carrier-amplifier bias power supply wiring. The one or more connection vias are connected to the shield pattern.

Abstract: A power amplification device includes: a first semiconductor chip including a first main surface and a second main surface; a first field-effect transistor, a first drain finger part, a plurality of first gate finger parts, and a source finger part; a sub-mount substrate including a third main surface and a fourth main surface; and a first filled via provided penetrating from the third main surface to the fourth main surface. In plan view, the first filled via has a rectangular shape. A long side direction of the first filled via is parallel to a long side direction of the plurality of first gate finger parts. In plan view, the first filled via is positioned to overlap part of one first gate finger part included in the plurality of first gate finger parts.

Abstract: A power amplification device includes: a first semiconductor chip including a first main surface and a second main surface; a first field-effect transistor, a first drain finger part, a plurality of first gate finger parts, and a source finger part; a sub-mount substrate including a third main surface and a fourth main surface; and a first filled via provided penetrating from the third main surface to the fourth main surface. In plan view, the first filled via has a rectangular shape. A long side direction of the first filled via is parallel to a long side direction of the plurality of first gate finger parts. In plan view, the first filled via is positioned to overlap part of one first gate finger part included in the plurality of first gate finger parts.

Abstract: A bias voltage is applied via a first resistance to the base of a first transistor, and a radio frequency signal is input via a first capacitor to the base of the first transistor. The bias voltage is applied via a second resistance to the base of a second transistor. The bias voltage is applied via a third resistance to the base of a third transistor, and the radio frequency signal RF is input via a third capacitor to the base of the third transistor. A first band rejection filter is provided between the base of the first transistor and the base of the second transistor. A second band rejection filter is provided between the base of the second transistor and the base of the third transistor. The collectors of the first to third transistors are connected in common and the emitters thereof are all grounded.

Abstract: A bias current to be supplied to an amplification circuit 60 is drawn out of a collector of a transistor Q11 of a bias circuit 10. The drawn-out bias current is input to a base of a transistor Q13 via an attenuation filter F2 and is output from an emitter of the transistor Q13 in the state where the voltage thereof is reduced by a level corresponding to Vbe. The attenuation filter F2 is conducted in a DC manner, and attenuates a component of a frequency fH(=2ft?fr) defined by a transmission frequency ft and a receiving frequency fr of a radio frequency signal. The bias current output from the emitter of the transistor Q13 is supplied to the amplification circuit 60 via an attenuation filter F1. The attenuation filter F1 is conducted in a DC manner, and attenuates a component of a frequency fL(=|fr?ft|).

Abstract: A bias voltage is applied via a first resistance to the base of a first transistor, and a radio frequency signal is input via a first capacitor to the base of the first transistor. The bias voltage is applied via a second resistance to the base of a second transistor. The bias voltage is applied via a third resistance to the base of a third transistor, and the radio frequency signal RF is input via a third capacitor to the base of the third transistor. A first band rejection filter is provided between the base of the first transistor and the base of the second transistor. A second band rejection filter is provided between the base of the second transistor and the base of the third transistor. The collectors of the first to third transistors are connected in common and the emitters thereof are all grounded.

Abstract: A bias current to be supplied to an amplification circuit 60 is drawn out of a collector of a transistor Q11 of a bias circuit 10. The drawn-out bias current is input to a base of a transistor Q13 via an attenuation filter F2 and is output from an emitter of the transistor Q13 in the state where the voltage thereof is reduced by a level corresponding to Vbe. The attenuation filter F2 is conducted in a DC manner, and attenuates a component of a frequency fH(=2ft?fr) defined by a transmission frequency ft and a receiving frequency fr of a radio frequency signal. The bias current output from the emitter of the transistor Q13 is supplied to the amplification circuit 60 via an attenuation filter attenuates a component of a frequency fL(=|fr?ft|).