Patents by Inventor Kazuhiko Ohmuro

Kazuhiko Ohmuro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8241515
    Abstract: A method of manufacturing a semiconductor device having a process for cleaning a semiconductor substrate after the semiconductor substrate is etched for patterning includes a first process of preparing the semiconductor substrate having a first temperature, a second process of setting the semiconductor substrate at a second temperature, a third process of etching the semiconductor substrate having the second temperature by etching liquid having a third temperature, a fourth process of cleaning the semiconductor substrate to which the etching liquid is adhered, by ultrapure water having a fourth temperature, wherein the second temperature is set at the range between the first and the third temperatures.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: August 14, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Kazuhiko Ohmuro, Takayuki Izumi, Ryoji Shigemasa, Tomoyuki Ohshima
  • Publication number: 20080242103
    Abstract: A method of manufacturing a semiconductor device having a process for cleaning a semiconductor substrate after the semiconductor substrate is etched for patterning includes a first process of preparing the semiconductor substrate having a first temperature, a second process of setting the semiconductor substrate at a second temperature, a third process of etching the semiconductor substrate having the second temperature by etching liquid having a third temperature, a fourth process of cleaning the semiconductor substrate to which the etching liquid is adhered, by ultrapure water having a fourth temperature, wherein the second temperature is set at the range between the first and the third temperatures.
    Type: Application
    Filed: March 12, 2008
    Publication date: October 2, 2008
    Inventors: Kazuhiko Ohmuro, Takayuki Izumi, Ryoji Shigemasa, Tomoyuki Ohshima
  • Patent number: 7235141
    Abstract: A lift-off procedure is provided which enables prevention of damage to a wiring pattern caused by contact of a metal being peeled off from a wafer with a wiring pattern at a time of lift-off procedure. A wafer having a surface on which a pattern is formed which contains a pattern portion to be removed is soaked into a chemical liquid at an angle at which the surface faces downward.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: June 26, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masaru Suzuki, Yoshiki Nitta, Kazuhiko Ohmuro
  • Patent number: 6962630
    Abstract: A lift-off procedure is provided which enables prevention of damage to a wiring pattern caused by contact of a metal being peeled off from a wafer with a wiring pattern at a time of lift-off procedure. A wafer having a surface on which a pattern is formed which contains a pattern portion to be removed is soaked into a chemical liquid at an angle at which the surface faces downward.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: November 8, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masaru Suzuki, Yoshiki Nitta, Kazuhiko Ohmuro
  • Publication number: 20050183753
    Abstract: A lift-off procedure is provided which enables prevention of damage to a wiring pattern caused by contact of a metal being peeled off from a wafer with a wiring pattern at a time of lift-off procedure. A wafer having a surface on which a pattern is formed which contains a pattern portion to be removed is soaked into a chemical liquid at an angle at which the surface faces downward.
    Type: Application
    Filed: April 22, 2005
    Publication date: August 25, 2005
    Inventors: Masaru Suzuki, Yoshiki Nitta, Kazuhiko Ohmuro
  • Publication number: 20030098046
    Abstract: A lift-off procedure is provided which enables prevention of damage to a wiring pattern caused by contact of a metal being peeled off from a wafer with a wiring pattern at a time of lift-off procedure. A wafer having a surface on which a pattern is formed which contains a pattern portion to be removed is soaked into a chemical liquid at an angle at which the surface faces downward.
    Type: Application
    Filed: October 3, 2002
    Publication date: May 29, 2003
    Inventors: Masaru Suzuki, Yoshiki Nitta, Kazuhiko Ohmuro
  • Patent number: 5994763
    Abstract: A wiring groove 5 and a via-hole 7 (9) is formed on the backside surface 3 of a semiconductor chip 1. A circuit electrode ER led from the circuit formed on the chip 1 and a boding pad BP, both of which are formed on the front surface of the semiconductor element, are electrically connected with each other with the help of a backside wiring formed in the wiring groove 5 and a penetration wiring 13 formed in the via-hole 7 (9). With such a wiring structure, it is made possible to form a wiring pattern using the wire having an adequate width, without increasing the size of the semiconductor chip 1.
    Type: Grant
    Filed: April 6, 1998
    Date of Patent: November 30, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kazuhiko Ohmuro
  • Patent number: 4905061
    Abstract: In a Schottky gate field effect transistor comprising a channel formed by doping donor ions in the surface layer of a compound semiconductor (e.g., GaAs) substrate and performing heat treatment, a Schottky gate electrode formed over the channel, and a source electrode and a drain electrode formed on the respective sides of the Schottky gate electrode, a first and a second regions are formed by implantation of ions which are to become carrier killers, to have respective concentration peaks shallower and deeper than the concentration peak of the donor ions of the channel.
    Type: Grant
    Filed: October 4, 1988
    Date of Patent: February 27, 1990
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Kazuhiko Ohmuro, Hiroshi Nakamura