Patents by Inventor Kazuhiko Okishima

Kazuhiko Okishima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9754915
    Abstract: In wire bonding in assembling of a semiconductor device, an Al wire is coupled to a lead section by a wedge which is a bonding tool, thereafter, the wedge is withdrawn from the top of the lead section and a cutter is lowered and the Al wire is cut off in this state. Lowering of the cutter is stopped at a point in time that a stopper which is lowered simultaneously with lowering of the cutter has truck against the lead section and cutting of the Al wire is terminated by stopping of lowering of the cutter.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: September 5, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuhiko Okishima
  • Publication number: 20160293569
    Abstract: In wire bonding in assembling of a semiconductor device, an Al wire is coupled to a lead section by a wedge which is a bonding tool, thereafter, the wedge is withdrawn from the top of the lead section and a cutter is lowered and the Al wire is cut off in this state. Lowering of the cutter is stopped at a point in time that a stopper which is lowered simultaneously with lowering of the cutter has truck against the lead section and cutting of the Al wire is terminated by stopping of lowering of the cutter.
    Type: Application
    Filed: March 3, 2016
    Publication date: October 6, 2016
    Inventor: Kazuhiko OKISHIMA
  • Patent number: 9368372
    Abstract: It includes the step of pressing a correcting tool against the main surface of a semiconductor chip while a solder material coated over a die pad is in a molten state and letting the solder material harden and the step of releasing the correcting tool from the chip and mounting the chip over the die pad. The correcting tool includes a first part having a first surface as a surface along the support surface of a support member for supporting the die pad and a second part having a second surface intersecting with the first surface. In the chip inclination correction process, the solder material is hardened while the first surface of the correcting tool is pressed against the upper surface of the chip and the second part of the correcting tool is pressed against the lead frame.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: June 14, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuhiko Okishima
  • Publication number: 20090294939
    Abstract: A lead frame and semiconductor device providing improved bond strength from wave bonding such as of wires in lead frames manufactured with depressed inner leads. The lead frame comprises an outer lead, an inner lead, a step difference section formed between the outer lead and inner lead, and an extended section extending from the inner lead towards the outer lead side. The extended section is provided to be adjacent to the step difference section. An acceptor clamp jig set on the lead frame includes a body, an inner lead support section and extended section support section respectively corresponding to the outer lead, the inner lead and the extended section. The outer lead is pressed from above by a retainer clamp jig. The extended section of the inner lead and the extension support section of the acceptor clamp jig prevent the tip of the inner lead from floating upward by acting together to accept and resist the tensile stress applied on the step difference section of the lead.
    Type: Application
    Filed: May 28, 2009
    Publication date: December 3, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Kazuhiko Okishima