Abstract: A non-volatile storage apparatus is configured to perform erase verify during an erase process in order to account for differences in erase speed. In order to reduce the time used to perform the erase process (which includes the erase verify), the erase verify operation is skipped for certain memory cells based on a system parameter. For example, when erasing a block of memory cells, a series of erase voltage pulses are applied to the NAND strings in outer sub-blocks and inner sub-blocks of the block. Erase verify is performed between erase voltage pulses for NAND strings in the outer sub-blocks while skipping erase verify for NAND strings in the inner sub-blocks. Performing erase verify between erase voltage pulses for NAND strings in the inner sub-blocks is started at a predetermined number of erase voltage pulses after the NAND strings in the outer sub-blocks successfully erase verify.

Abstract: A non-volatile storage apparatus is configured to perform erase verify during an erase process in order to account for differences in erase speed. In order to reduce the time used to perform the erase process (which includes the erase verify), the erase verify operation is skipped for certain memory cells based on a system parameter. For example, when erasing a block of memory cells, a series of erase voltage pulses are applied to the NAND strings in outer sub-blocks and inner sub-blocks of the block. Erase verify is performed between erase voltage pulses for NAND strings in the outer sub-blocks while skipping erase verify for NAND strings in the inner sub-blocks. Performing erase verify between erase voltage pulses for NAND strings in the inner sub-blocks is started at a predetermined number of erase voltage pulses after the NAND strings in the outer sub-blocks successfully erase verify.

Abstract: A non-volatile storage apparatus is configured to perform erase verify during an erase process in order to account for differences in erase speed. In order to reduce the time used to perform the erase process (which includes the erase verify), the erase verify operation is skipped for certain memory cells based on a system parameter. For example, when erasing a block of memory cells, a series of erase voltage pulses are applied to the NAND strings in outer sub-blocks and inner sub-blocks of the block. Erase verify is performed between erase voltage pulses for NAND strings in the outer sub-blocks while skipping erase verify for NAND strings in the inner sub-blocks. Performing erase verify between erase voltage pulses for NAND strings in the inner sub-blocks is started at a predetermined number of erase voltage pulses after the NAND strings in the outer sub-blocks successfully erase verify.

Abstract: A non-volatile storage apparatus is configured to perform erase verify during an erase process in order to account for differences in erase speed. In order to reduce the time used to perform the erase process (which includes the erase verify), the erase verify operation is skipped for certain memory cells based on a system parameter. For example, when erasing a block of memory cells, a series of erase voltage pulses are applied to the NAND strings in outer sub-blocks and inner sub-blocks of the block. Erase verify is performed between erase voltage pulses for NAND strings in the outer sub-blocks while skipping erase verify for NAND strings in the inner sub-blocks. Performing erase verify between erase voltage pulses for NAND strings in the inner sub-blocks is started at a predetermined number of erase voltage pulses after the NAND strings in the outer sub-blocks successfully erase verify.

Abstract: A trench gate transistor whose gate changes the depth thereof intermittently in the gate width direction, has a first offset region and a second offset region formed below the source and drain, respectively. The sum of length measurements of the underlying portion of the second offset region measured from the lower corner of the trench in a direction parallel to the substrate and in a direction perpendicular to the substrate is 0.1 ?m or greater.

Abstract: A semiconductor device contains a first transistor including a single trench which is formed on a substrate between a source region and a drain region and a gate electrode which is formed in the single trench, a second transistor including at least two trenches which are formed on the substrate between a source region and a drain region and a gate electrode which is formed in the at least two trenches, and also contains a device isolation insulating which isolates the region in which the transistor is formed. The first transistor has first distance between the single trench and the device isolation insulating film and the second transistor has second distance between the adjoining trenches, such the first distance is less than the second distance in a gate width direction.

Abstract: A semiconductor device contains a first transistor including a single trench which is formed on a substrate between a source region and a drain region and a gate electrode which is formed in the single trench, a second transistor including at least two trenches which are formed on the substrate between a source region and a drain region and a gate electrode which is formed in the at least two trenches, and also contains a device isolation insulating which isolates the region in which the transistor is formed. The first transistor has first distance between the single trench and the device isolation insulating film and the second transistor has second distance between the adjoining trenches, such the first distance is less than the second distance in a gate width direction.

Abstract: A trench gate transistor whose gate changes the depth thereof intermittently in the gate width direction, has a first offset region and a second offset region formed below the source and drain, respectively. The sum of length measurements of the underlying portion of the second offset region measured from the lower corner of the trench in a direction parallel to the substrate and in a direction perpendicular to the substrate is 0.1 ?m or greater.

Abstract: Effective area of a capacitor is to be increased while suppressing increase in number of manufacturing steps. In a semiconductor device, a silicon substrate includes a plurality of first recessed portions having a first depth from the main surface thereof, a second recessed portion provided in a region other than the first recessed portion and having a second depth from the main surface, and a third recessed portion provided in at least one of the plurality of first recessed portions and having a third depth from the bottom portion of the first recessed portion. The second recessed portion and the third recessed portion have the same depth, and a decoupling condenser is provided so as to fill the at least one of the first recessed portion and the third recessed portion provided therein, and an isolation insulating layer is provided so as to fill the remaining first recessed portions, and the second recessed portion is filled with a gate electrode.

Abstract: A semiconductor storage device in which product cost is reduced includes a memory cell section (cells belonging to word lines) and a bypass section (cells belonging to bypass word lines). The memory cell section has a select gate, floating gates, a first diffusion region, a second diffusion region and a first control gate. The bypass section has the first select gate, the first diffusion region, the second diffusion region and a second control gate. The second control gate controls a channel in an area between the select gate and the first diffusion region or between the select gate and the second diffusion region. The channel of the bypass section becomes a current supply path when a cell of the memory cell section is read out.

Abstract: Effective area of a capacitor is to be increased while suppressing increase in number of manufacturing steps. In a semiconductor device, a silicon substrate includes a plurality of first recessed portions having a first depth from the main surface thereof, a second recessed portion provided in a region other than the first recessed portion and having a second depth from the main surface, and a third recessed portion provided in at least one of the plurality of first recessed portions and having a third depth from the bottom portion of the first recessed portion. The second recessed portion and the third recessed portion have the same depth, and a decoupling condenser is provided so as to fill the at least one of the first recessed portion and the third recessed portion provided therein, and an isolation insulating layer is provided so as to fill the remaining first recessed portions, and the second recessed portion is filled with a gate electrode.

Abstract: A semiconductor memory device with improved operational reliability, and a method for fabricating the device. The semiconductor memory device includes a select gate 3a, arranged in a first area on a substrate 1, floating gates 6a arranged in a second are,a adjacent to the first area, first and second diffusion areas 7a, 7b arranged in a third area adjacent to the second area, and a control gate 11 arranged on the top of the floating gates 6a. The upper end faces of the floating gates 6a are planarized.

Abstract: A semiconductor storage device in which product cost is reduced includes a memory cell section (cells belonging to word lines) and a bypass section (cells belonging to bypass word lines). The memory cell section has a select gate, floating gates, a first diffusion region, a second diffusion region and a first control gate. The bypass section has the first select gate, the first diffusion region, the second diffusion region and a second control gate. The second control gate controls a channel in an area between the select gate and the first diffusion region or between the select gate and the second diffusion region. The channel of the bypass section becomes a current supply path when a cell of the memory cell section is read out.

Abstract: A lower electrode in a capacitive element area is formed on a field oxide film in self-alignment with trenches, so that the lower electrode and floating gate electrodes in a memory cell area can simultaneously be formed in one process. The lower electrode is surrounded by the trenches defined in the field oxide film. An upper electrode formed together with a control gate electrode in one process is disposed over the lower electrode with an insulating film, which is formed together with an intergate insulating film in the memory cell area in one process, interposed therebetween. With this arrangement, a semiconductor device having a capacitive element for use in a charge pump circuit or the like has its chip area prevented from being increased, allow the capacitive element to have a highly accurate capacitance, and can be manufactured in a reduced number of fabrication steps.

Abstract: A lower electrode in a capacitive element area is formed on a field oxide film in self-alignment with trenches, so that the lower electrode and floating gate electrodes in a memory cell area can simultaneously be formed in one process. The lower electrode is surrounded by the trenches defined in the field oxide film. An upper electrode formed together with a control gate electrode in one process is disposed over the lower electrode with an insulating film, which is formed together with an intergate insulating film in the memory cell area in one process, interposed therebetween. With this arrangement, a semiconductor device having a capacitive element for use in a charge pump circuit or the like has its chip area prevented from being increased, allow the capacitive element to have a highly accurate capacitance, and can be manufactured in a reduced number of fabrication steps.

Abstract: The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lover erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole. However, when only some memory cells of a group have a higher erase speed, an excessive erase requiring electric charge supply occurs only in some memories and accordingly, it is possible to rapidly complete the data.

Abstract: The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lower erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole.

Abstract: A semiconductor device having a multi-layer wiring structure is provided. In the device, a void for reducing parasitic capacitance between wirings of the device is formed in an interlayer insulating film. When a contact holes passes through the void, adjacent bit lines would ordinarily be short-circuited through metal entering the void between the contact holes. However, in the semiconductor device, a side wall insulating film is formed on an inner wall of a contact holes. Thus, the contact holes can connect a diffusion layer and a bit line and can intersect a void without creating a short circuit. Thus, it is possible to reduce short circuits occurring through the contact holes between the bit lines and to reduce parasitic capacitance between the wirings.

Abstract: The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lower erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole.

Abstract: A manufacturing method for a semiconductor memory device is provided, which comprises the steps of forming buried layers 2 for bit lines, forming gate electrodes 3 which cross the buried layers 2 at a right angle, and depositing an interlayer insulating film 5 (C). Ion injection windows are opened through the interlayer insulating film on the channel regions of every memory cell using a regular reticule pattern (D). A photoresist film 7 in conformity with the code pattern is formed and ion injected layer 8 is formed at a prescribed channel region for writing information. It becomes possible to form the ion injection windows without being affected by the density of the code pattern and to inject ions at low energy. Therefore, the transverse broadening of the injection ion beam can be prevented, to prevent fluctuations of the threshold voltage of the non-selected cells.