Patents by Inventor Kazuhiko SEGI

Kazuhiko SEGI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230413568
    Abstract: In a memory region, a memory-region first portion in which no raised epitaxial layer is formed, a memory-region second portion in which a first raised epitaxial layer is formed, and a memory-region third portion in which a second raised epitaxial layer is formed are defined. In the memory-region first portion, a first-diffusion-layer first portion of a memory transistor and a second-diffusion-layer first portion of a select transistor are formed. A first-diffusion-layer second portion of the memory transistor is formed in the first raised epitaxial layer. A second-diffusion-layer second portion of the select transistor is formed in the second raised epitaxial layer.
    Type: Application
    Filed: April 20, 2023
    Publication date: December 21, 2023
    Inventors: Kazuhiko SEGI, Yoshiyuki KAWASHIMA
  • Patent number: 11742199
    Abstract: First, an offset spacer including a stacked film of insulating films is formed on the upper surface of the semiconductor layer, the side surface of the gate electrode, and the side surface of the cap film. Next, a part of the insulating films is removed to expose the upper surface of the semiconductor layer. Next, in a state where the side surface of the gate electrode is covered with the insulating films, an epitaxial layer is formed on the exposed upper surface of the semiconductor layer. Here, among the offset spacers, the insulating film which is a silicon nitride film is formed at a position closest to the gate electrode, and the position of the upper end of the insulating film formed on the side surface of the gate electrode is higher than the position of the upper surface of the gate electrode.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: August 29, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuhiko Segi
  • Publication number: 20210210337
    Abstract: First, an offset spacer including a stacked film of insulating films is formed on the upper surface of the semiconductor layer, the side surface of the gate electrode, and the side surface of the cap film. Next, a part of the insulating films is removed to expose the upper surface of the semiconductor layer. Next, in a state where the side surface of the gate electrode is covered with the insulating films, an epitaxial layer is formed on the exposed upper surface of the semiconductor layer. Here, among the offset spacers, the insulating film which is a silicon nitride film is formed at a position closest to the gate electrode, and the position of the upper end of the insulating film formed on the side surface of the gate electrode is higher than the position of the upper surface of the gate electrode.
    Type: Application
    Filed: March 16, 2021
    Publication date: July 8, 2021
    Inventor: Kazuhiko SEGI
  • Patent number: 10985012
    Abstract: First, an offset spacer including a stacked film of insulating films is formed on the upper surface of the semiconductor layer, the side surface of the gate electrode, and the side surface of the cap film. Next, a part of the insulating films is removed to expose the upper surface of the semiconductor layer. Next, in a state where the side surface of the gate electrode is covered with the insulating films, an epitaxial layer is formed on the exposed upper surface of the semiconductor layer. Here, among the offset spacers, the insulating film which is a silicon nitride film is formed at a position closest to the gate electrode, and the position of the upper end of the insulating film formed on the side surface of the gate electrode is higher than the position of the upper surface of the gate electrode.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: April 20, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuhiko Segi
  • Publication number: 20190371593
    Abstract: First, an offset spacer including a stacked film of insulating films is formed on the upper surface of the semiconductor layer, the side surface of the gate electrode, and the side surface of the cap film. Next, a part of the insulating films is removed to expose the upper surface of the semiconductor layer. Next, in a state where the side surface of the gate electrode is covered with the insulating films, an epitaxial layer is formed on the exposed upper surface of the semiconductor layer. Here, among the offset spacers, the insulating film which is a silicon nitride film is formed at a position closest to the gate electrode, and the position of the upper end of the insulating film formed on the side surface of the gate electrode is higher than the position of the upper surface of the gate electrode.
    Type: Application
    Filed: May 8, 2019
    Publication date: December 5, 2019
    Inventor: Kazuhiko SEGI