Abstract: A data processing system comprises a microprocessor having a burst mode transfer function, a memory receiving an address supplied from said microprocessor to output data designated by the received address, an address decoder receiving and decoding said address supplied from said microprocessor, and a memory control circuit receiving an output of said address decoder and control signals from said microprocessor, for controlling said memory. The system is configured to generate a burst mode transfer period designating signal indicating a period of a burst mode transfer, so that a synchronous burst mode transfer is performed in accordance with the period of the burst mode transfer designated by said burst mode transfer period designating signal, so as to cause said microcomputer to fetch data transferred from said memory by the synchronous burst mode transfer.

Abstract: A quick-peelable fruit protective wrap comprises gadgets formed by folding both lateral sides of the wrap outside in, a nearly U-shaped notch portion forming a pair of strips with both sides of the opening portion in the top connected together to span over a branch, and a base portion with the gadgets also adhered in one body, and has pores on the whole surface, the pores are formed in ovals with the long diameters directed along the opening and base portions and the base portion of the wrap is of reinforced structure, thereby permitting a fruit to be taken out at a stretch from the wrap and simultaneously the wrap to be removed from the branch bearing the fruit.

Abstract: A cache memory unit for use in a multiprocessor. The unit includes a data memory, a tag memory, a valid flag section, and an address bus, a comparator, and a clear signal producing section which produces a monitoring clear signal based on an output from the comparator and a monitoring strobe signal. The valid flag section receives the monitoring clear signal from the clear signal producing section. The cache memory unit further includes a monitoring strobe signal activating section which causes the monitoring strobe signal to be inputted to the clear signal producing section active or inactive whereby the valid flag section is cleared or prohibited from being cleared. The monitoring strobe signal activating section is reset when the operation enters into an in-circuit emulator (ICE) program and is set when the operation is freed from the ICE program. The cache memory unit enables the system to be debugged precisely without no delay in the execution of time.