Patents by Inventor Kazuhiko Tokuda
Kazuhiko Tokuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9842179Abstract: A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute a process is provided. The process includes: generating a second characteristic model from a plurality of first characteristic models by using a maximum value and a minimum value of a prescribed parameter in the plurality of first characteristic models; executing simulation by using the second characteristic model; calculating a plurality of first margins for an evaluation item according to a result of the simulation; calculating a plurality of second margins for the evaluation item with respect to each of the first characteristic models; calculating a ratio of each of the plurality of second margins to a maximum margin of the plurality at first margins; and ranking the plurality of first characteristic models according to the ratio.Type: GrantFiled: January 20, 2016Date of Patent: December 12, 2017Assignee: FUJITSU LIMITEDInventor: Kazuhiko Tokuda
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Publication number: 20160292335Abstract: A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute a process is provided. The process includes: generating a second characteristic model from a plurality of first characteristic models by using a maximum value and a minimum value of a prescribed parameter in the plurality of first characteristic models; executing simulation by using the second characteristic model; calculating a plurality of first margins for an evaluation item according to a result of the simulation; calculating a plurality of second margins for the evaluation item with respect to each of the first characteristic models; calculating a ratio of each of the plurality of second margins to a maximum margin of the plurality at first margins; and ranking the plurality of first characteristic models according to the ratio.Type: ApplicationFiled: January 20, 2016Publication date: October 6, 2016Applicant: FUJITSU LIMITEDInventor: Kazuhiko TOKUDA
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Patent number: 9307642Abstract: A printed-board includes a first conductor-layer, a second conductor-layer provided to a layer different from the first conductor-layer, an insulation-layer provided between the first conductor-layer and the second conductor-layer, a plurality of through-holes that pass through the first conductor-layer, the second conductor-layer, and the insulation-layer, and a plurality of vias that are formed in the plurality of through-holes, respectively, and couple the first conductor-layer and the second conductor-layer, each of the plurality of vias including a conductor portion that occupies part of an internal space of the through-hole, and a non-conductor portion that occupies remaining part of the internal space, wherein in a given pair of vias adjacent to each other, the conductor portion of one of the pair of vias is arranged so as to face the non-conductor portion of another one of the pair of vias.Type: GrantFiled: December 17, 2013Date of Patent: April 5, 2016Assignee: FUJITSU LIMITEDInventor: Kazuhiko Tokuda
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Publication number: 20140268618Abstract: A printed-board includes a first conductor-layer, a second conductor-layer provided to a layer different from the first conductor-layer, an insulation-layer provided between the first conductor-layer and the second conductor-layer, a plurality of through-holes that pass through the first conductor-layer, the second conductor-layer, and the insulation-layer, and a plurality of vias that are formed in the plurality of through-holes, respectively, and couple the first conductor-layer and the second conductor-layer, each of the plurality of vias including a conductor portion that occupies part of an internal space of the through-hole, and a non-conductor portion that occupies remaining part of the internal space, wherein in a given pair of vias adjacent to each other, the conductor portion of one of the pair of vias is arranged so as to face the non-conductor portion of another one of the pair of vias.Type: ApplicationFiled: December 17, 2013Publication date: September 18, 2014Applicant: FUJITSU LIMITEDInventor: Kazuhiko TOKUDA
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Patent number: 7954076Abstract: A transmission delay analyzing apparatus includes: a first acquisition section that acquires a noise waveform from among waveforms which propagate in a first transmission line and acquired by a receiving circuit; a first calculation section that calculates a noise peak level which is the peak level of the noise waveform acquired by the first acquisition section; a second acquisition section that acquires a signal waveform free from noise from among the waveforms which propagate in the first transmission line and acquired by the receiving circuit; and a second calculation section that calculates a delay variation of a transmitted signal based on the signal waveform acquired by the second acquisition section, a threshold for determining the level of a signal that the receiving circuit has received from the first transmission line, and the noise peak level calculated by the first calculation section.Type: GrantFiled: December 9, 2008Date of Patent: May 31, 2011Assignee: Fujitsu LimitedInventor: Kazuhiko Tokuda
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Publication number: 20090298438Abstract: A transmission delay analyzing apparatus includes: a first acquisition section that acquires a noise waveform from among waveforms which propagate in a first transmission line and acquired by a receiving circuit; a first calculation section that calculates a noise peak level which is the peak level of the noise waveform acquired by the first acquisition section; a second acquisition section that acquires a signal waveform free from noise from among the waveforms which propagate in the first transmission line and acquired by the receiving circuit; and a second calculation section that calculates a delay variation of a transmitted signal based on the signal waveform acquired by the second acquisition section, a threshold for determining the level of a signal that the receiving circuit has received from the first transmission line, and the noise peak level calculated by the first calculation section.Type: ApplicationFiled: December 9, 2008Publication date: December 3, 2009Applicant: FUJITSU LIMITEDInventor: Kazuhiko TOKUDA
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Patent number: 7398504Abstract: From design information on a circuit board a wiring designation unit designates a wiring model for signal analysis. A first analysis unit generates, through a 3-D electromagnetic analysis, a first output waveform received at a receiving end of a wiring model when a first input signal pattern changing from 0 to 1 is input to a sending end of the wiring model. A second analysis unit generates, through the 3-D electromagnetic analysis, a second output waveform received at the receiving end of the wiring model when a second input signal pattern changing from 1 to 0 is input to the sending end of the wiring model. An output waveform generation unit selects the first output waveform at bit 1 of a random signal of about 100 bits and selects the second output waveform at bit 0 thereof to generate for a predetermined bit count the first output waveform or the second output waveform selected with each bit position as a starting point.Type: GrantFiled: August 15, 2005Date of Patent: July 8, 2008Assignee: Fujitsu LimitedInventor: Kazuhiko Tokuda
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Patent number: 7280953Abstract: A noise countermeasure determination method includes the step of obtaining an analyzing circuit judgement result by judging acceptability of the analyzing circuit based on a comparison of features of the analyzing circuit and transmission circuit topologies, and outputting an improvement proposal for making the analyzing circuit closer to one of basic types of the transmission circuit topologies depending on the analyzing circuit judgement result.Type: GrantFiled: June 18, 2001Date of Patent: October 9, 2007Assignee: Fujitsu LimitedInventors: Shogo Fujimori, Yasuhiro Yamashita, Ryoji Yamada, Masaki Tosaka, Kazuhiko Tokuda, Jiro Yoneda, Makoto Suwada, Tatsuo Koizumi
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Patent number: 7103525Abstract: The high-frequency-corresponding simulation apparatus includes a control section that calculates a sum of the DC resistance value and skin resistance value of each of a plurality of elements corresponding to wiring patterns in accordance with circuit deign information, sorts resistance values corresponding to the elements by using a high-frequency element delay as a key when the total resistance value is equal to or larger than a first threshold value, integrates resistance values starting with a resistance value having the smallest high-frequency element delay, and which determines whether the result of the integration reaches a value immediately before a second threshold value whenever the integration is executed and a RLC-model analysis section.Type: GrantFiled: August 15, 2001Date of Patent: September 5, 2006Assignee: Fujitsu LimitedInventors: Makoto Suwada, Tatsuo Koizumi, Masaki Tosaka, Kazuhiko Tokuda, Jiro Yoneda
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Patent number: 7065480Abstract: A noise countermeasure determination method includes the steps of calculating recommended circuit information considered to minimize a noise by use of at least one formula, based on input circuit information amounting to at least one net of a target circuit which is to be subjected to a noise analysis, and comparing the input circuit information and the recommended circuit information, and determining a differing portion of the recommended circuit information differing from the input circuit information, as noise countermeasures.Type: GrantFiled: December 29, 2000Date of Patent: June 20, 2006Assignee: Fujitsu LimitedInventors: Shogo Fujimori, Yasuhiro Yamashita, Ryoji Yamada, Masaki Tosaka, Kazuhiko Tokuda, Jiro Yoneda, Makoto Suwada, Tatsuo Koizumi
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Patent number: 7035783Abstract: In a simulation considering a skin effect, a signal conductor is vertically and horizontally divided by faces parallel to the surface of the signal conductor, which are set so that intervals are smaller as the faces are nearer to the surface, and larger as the faces are farther from the surface. Also a ground conductor is vertically divided with a similar method, and an integration calculation is made, so that the resistance of the signal conductor, which corresponds to a given frequency, is obtained.Type: GrantFiled: January 23, 2002Date of Patent: April 25, 2006Assignee: Fujitsu LImitedInventors: Megumi Nagata, Masaki Tosaka, Kazuhiko Tokuda, Hiroyuki Orihara, Hikoyuki Kawata
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Publication number: 20050273740Abstract: From design information on a circuit board a wiring designation unit designates a wiring model for signal analysis. A first analysis unit generates, through a 3-D electromagnetic analysis, a first output waveform received at a receiving end of a wiring model when a first input signal pattern changing from 0 to 1 is input to a sending end of the wiring model. A second analysis unit generates, through the 3-D electromagnetic analysis, a second output waveform received at the receiving end of the wiring model when a second input signal pattern changing from 1 to 0 is input to the sending end of the wiring model. An output waveform generation unit selects the first output waveform at bit 1 of a random signal of about 100 bits and selects the second output waveform at bit 0 thereof to generate for a predetermined bit count the first output waveform or the second output waveform selected with each bit position as a starting point.Type: ApplicationFiled: August 15, 2005Publication date: December 8, 2005Applicant: FUJITSU LIMITEDInventor: Kazuhiko Tokuda
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Patent number: 6925430Abstract: The apparatus includes the wiring-model generation section that generates a wiring model in accordance with high-frequency-circuit design information; the random-pattern analysis section that generates and analyzes a dummy random-pattern waveform for transmitting a wiring model in accordance with a command including the bit information of a random-pattern waveform and a differential waveform corresponding to the dummy random-pattern waveform; and the skew analysis section that skews a random-pattern waveform or differential waveform in accordance with a preset skew width.Type: GrantFiled: September 5, 2001Date of Patent: August 2, 2005Assignee: Fujitsu LimitedInventors: Makoto Suwada, Tatsuo Koizumi, Masaki Tosaka, Kazuhiko Tokuda, Jiro Yoneda
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Patent number: 6662132Abstract: A noise analyzing method analyzes a crosstalk noise based on circuit data in which buses having the same signal transmitting direction and buses having opposite signal transmitting directions are distinguished from each other, by analyzing the crosstalk noise only for the same signal transmitting direction with respect to the buses having the same signal transmitting direction.Type: GrantFiled: December 11, 2000Date of Patent: December 9, 2003Assignee: Fujitsu LimitedInventors: Yasuhiro Yamashita, Shogo Fujimori, Ryoji Yamada, Kazuhiko Tokuda, Makoto Suwada, Masaki Tosaka, Jiro Yoneda, Yoshiyuki Iwakura, Kazunari Gotou
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Publication number: 20030083853Abstract: In a simulation considering a skin effect, a signal conductor is vertically and horizontally divided by faces parallel to the surface of the signal conductor, which are set so that intervals are smaller as the faces are nearer to the surface, and larger as the faces are farther from the surface. Also a ground conductor is vertically divided with a similar method, and an integration calculation is made, so that the resistance of the signal conductor, which corresponds to a given frequency, is obtained.Type: ApplicationFiled: January 23, 2002Publication date: May 1, 2003Applicant: Fujitsu LimitedInventors: Megumi Nagata, Masaki Tosaka, Kazuhiko Tokuda, Hiroyuki Orihara, Hikoyuki Kawata
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Publication number: 20020032556Abstract: The high-frequency-corresponding simulation apparatus includes a control section that calculates a sum of the DC resistance value and skin resistance value of each of a plurality of elements corresponding to wiring patterns in accordance with circuit deign information, sorts resistance values corresponding to the elements by using a high-frequency element delay as a key when the total resistance value is equal to or larger than a first threshold value, integrates resistance values starting with a resistance value having the smallest high-frequency element delay, and which determines whether the result of the integration reaches a value immediately before a second threshold value whenever the integration is executed and a RLC-model analysis section.Type: ApplicationFiled: August 15, 2001Publication date: March 14, 2002Applicant: Fujitsu LimitedInventors: Makoto Suwada, Tatsuo Koizumi, Masaki Tosaka, Kazuhiko Tokuda, Jiro Yoneda
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Publication number: 20020032555Abstract: The apparatus includes the wiring-model generation section that generates a wiring model in accordance with high-frequency-circuit design information; the random-pattern analysis section that generates and analyzes a dummy random-pattern waveform for transmitting a wiring model in accordance with a command including the bit information of a random-pattern waveform and a differential waveform corresponding to the dummy random-pattern waveform; and the skew analysis section that skews a random-pattern waveform or differential waveform in accordance with a preset skew width.Type: ApplicationFiled: September 5, 2001Publication date: March 14, 2002Applicant: Fujitsu LimitedInventors: Makoto Suwada, Tatsuo Koizumi, Masaki Tosaka, Kazuhiko Tokuda, Jiro Yoneda
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Publication number: 20020027021Abstract: A printed circuit board includes a first wiring line and a second wiring line spaced apart from the first wiring line. The first wiring line has a first portion having a surface which faces the second wiring line and is smaller in area than that of the second portion, so that a crosstalk noise between the first portion of the first wiring line and the second wiring line can be reduced.Type: ApplicationFiled: August 14, 2001Publication date: March 7, 2002Applicant: FUJITSU LIMITEDInventor: Kazuhiko Tokuda
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Patent number: 6340798Abstract: A printed circuit board includes a first wiring line and a second wiring line spaced apart from the first wiring line. The first wiring line has a first portion having a surface which faces the second wiring line and is smaller in area than that of the second portion, so that a crosstalk noise between the first portion of the first wiring line and the second wiring line can be reduced.Type: GrantFiled: August 1, 2000Date of Patent: January 22, 2002Assignee: Fujitsu LimitedInventor: Kazuhiko Tokuda
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Publication number: 20020007253Abstract: A noise analyzing method analyzes a crosstalk noise based on circuit data in which buses having the same signal transmitting direction and buses having opposite signal transmitting directions are distinguished from each other, by analyzing the crosstalk noise only for the same signal transmitting direction with respect to the buses having the same signal transmitting direction.Type: ApplicationFiled: December 11, 2000Publication date: January 17, 2002Inventors: Yasuhiro Yamashita, Shogo Fujimori, Ryoji Yamada, Kazuhiko Tokuda, Makoto Suwada, Masaki Tosaka, Jiro Yoneda, Yoshiyuki Iwakura, Kazunari Gotou