Abstract: In one embodiment of the present invention, a high withstand voltage transistor is disclosed having small sizes including an element isolating region. The semiconductor device is provided with the element isolating region formed on a semiconductor substrate; an active region demarcated by the element isolating region; a gate electrode formed on the semiconductor substrate in the active region by having a gate insulating film in between; a channel region arranged in the semiconductor substrate under the gate electrode; a source region and a drain region positioned on the both sides of the gate electrode; and a drift region positioned between one of or both of the source region and the drain region and the channel region. One of or both of the source region and the drain region are at least partially positioned on the element isolating region, and are connected with the channel region through the drift region.

Abstract: In one embodiment of the present invention, a high withstand voltage transistor is disclosed having small sizes including an element isolating region. The semiconductor device is provided with the element isolating region formed on a semiconductor substrate; an active region demarcated by the element isolating region; a gate electrode formed on the semiconductor substrate in the active region by having a gate insulating film in between; a channel region arranged in the semiconductor substrate under the gate electrode; a source region and a drain region positioned on the both sides of the gate electrode; and a drift region positioned between one of or both of the source region and the drain region and the channel region. One of or both of the source region and the drain region are at least partially positioned on the element isolating region, and are connected with the channel region through the drift region.

Abstract: A process for producing a semiconductor device comprises the steps of: (a) forming a gate electrode on N channel and P channel transistors forming regions (N-Tr region and P-Tr region) on a semiconductor substrate; (b) forming a side wall spacer on a side wall of the gate electrode; (c) covering the P-Tr region with a resist, and forming a source/drain region on the N-Tr region by ion implantation using the resist, the gate electrode and the side wall spacer as a mask; (d) removing a part of the side wall spacer of the gate electrode in the N-Tr region; (e) forming an LDD region on the N-Tr region by ion implantation using the resist, the gate electrode and the resulting side wall spacer as a mask; (f) removing the resist; (g) covering the N-Tr region with a resist, and forming a source/drain region on the P-Tr region by ion implantation using the resist, the gate electrode and the side wall spacer as a mask; (h) removing a part of the side wall spacer of the gate electrode in the P-Tr region; and (i) forming

Abstract: A process for fabricating a semiconductor device basically includes forming a boron implanted layer intended to be a base region by implanting boron ions to a substrate through a first opening, implanting fluorine ions to the substrate through a second opening serving to define an emitter-inner base formation region beneath the second opening and in the boron implanted layer to lower the boron ion concentration of that region only thereby lowering the peak carrier concentration of an inner base region than that of an emitter region to be formed later, and doping the region defined by a third opening with arsenic ions to form the emitter region with the inner base region underlying.