Patents by Inventor Kazuhira YAMADA

Kazuhira YAMADA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Logic verifying apparatus, and computer-readable recording medium in which logic verifying program is stored
    Patent number: 8806149
    Abstract: A logic verifying apparatus includes a second processor corresponding to a first processor to be verified; and one or more second controllers corresponding to first controllers to be verified, the number of which is less than that of the first controllers, control a second access to a memory, the access being made by the second processor, the second processor and the second controllers serving as elements in the verification model. The second processor includes a storing unit that stores information that assigns one or more of the second controllers that is to be used as the verification model; and a converting unit that converts a first address into a second address, the first address indicating an entity that the second processor is to access through the one second controller assigned by the information stored in the storing unit such that the second processor access to the memory.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: August 12, 2014
    Assignee: Fujitsu Limited
    Inventor: Kazuhira Yamada
  • LOGIC VERIFYING APPARATUS, AND COMPUTER-READABLE RECORDING MEDIUM IN WHICH LOGIC VERIFYING PROGRAM IS STORED
    Publication number: 20120047335
    Abstract: A logic verifying apparatus includes a second processor corresponding to a first processor to be verified; and one or more second controllers corresponding to first controllers to be verified, the number of which is less than that of the first controllers, control a second access to a memory, the access being made by the second processor, the second processor and the second controllers serving as elements in the verification model. The second processor includes a storing unit that stores information that assigns one or more of the second controllers that is to be used as the verification model; and a converting unit that converts a first address into a second address, the first address indicating an entity that the second processor is to access through the one second controller assigned by the information stored in the storing unit such that the second processor access to the memory.
    Type: Application
    Filed: May 12, 2011
    Publication date: February 23, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Kazuhira YAMADA