Patents by Inventor Kazuhiro Hata
Kazuhiro Hata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240069826Abstract: Provided is a printing apparatus capable of communicating with an information processing apparatus which displays a remaining amount of a color material in the printing apparatus on a display region based on information sent from the printing apparatus. The printing apparatus receives an obtaining request to obtain information on the printing apparatus from the information processing apparatus, and controls a display color of the color material such that a color difference between the display color of the color material and a background color of the display region becomes more than or equal to a predetermined value. The printing apparatus sends information on the printing apparatus including the controlled display color and the remaining amount of the color material to the information processing apparatus as a response to the obtaining request.Type: ApplicationFiled: July 14, 2023Publication date: February 29, 2024Inventor: Kazuhiro Hata
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Patent number: 10123681Abstract: An endoscope insertion shape observation apparatus includes an endoscope, a magnetic field generation coil provided at an insertion portion of the endoscope and configured to generate a magnetic field, an antenna unit configured to receive a coil signal from the magnetic field generation coil, a bending portion configured to bend the insertion portion, a bending drive section configured to drive the bending portion to bend, an insertion shape processing circuit configured to generate an insertion shape of the endoscope inserted into a subject according to a signal received from the antenna unit, a touch panel configured to display a generation result of the insertion shape processing circuit and be able to perform touch operation, and a drive section control circuit configured to control a drive amount of the bending drive section based on the touch operation on a desired location of the insertion shape displayed on the touch panel.Type: GrantFiled: November 16, 2016Date of Patent: November 13, 2018Assignee: OLYMPUS CORPORATIONInventors: Keijiro Omoto, Takashi Yamashita, Kensuke Miyake, Kazuhiro Hata, Fumiyuki Onoda
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Publication number: 20170055809Abstract: An endoscope insertion shape observation apparatus includes an endoscope, a magnetic field generation coil provided at an insertion portion of the endoscope and configured to generate a magnetic field, an antenna unit configured to receive a coil signal from the magnetic field generation coil, a bending portion configured to bend the insertion portion, a bending drive section configured to drive the bending portion to bend, an insertion shape processing circuit configured to generate an insertion shape of the endoscope inserted into a subject according to a signal received from the antenna unit, a touch panel configured to display a generation result of the insertion shape processing circuit and be able to perform touch operation, and a drive section control circuit configured to control a drive amount of the bending drive section based on the touch operation on a desired location of the insertion shape displayed on the touch panel.Type: ApplicationFiled: November 16, 2016Publication date: March 2, 2017Applicant: OLYMPUS CORPORATIONInventors: Keijiro OMOTO, Takashi YAMASHITA, Kensuke MIYAKE, Kazuhiro HATA, Fumiyuki ONODA
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Publication number: 20160331210Abstract: An insertion apparatus includes an insertion portion, a power spiral tube provided with a spiral fin portion configured to extend in a spiral shape, the power spiral tube being provided on an outer circumferential direction side of the insertion portion so as to be rotatable with respect to the insertion portion around a longitudinal axis, a first motor configured to generate a drive force to rotate the power spiral tube, an operation section provided on a proximal end side of the insertion portion, a second motor configured to generate a drive force to rotate the insertion portion pivotably held to the operation section, and a second motor drive circuit configured to calculate torque to be added to the power spiral tube and perform control so as to drive the second motor in accordance with torque added to the first motor.Type: ApplicationFiled: July 27, 2016Publication date: November 17, 2016Applicant: OLYMPUS CORPORATIONInventors: Fumiyuki ONODA, Takashi YAMASHITA, Keijiro OMOTO, Kensuke MIYAKE, Kazuhiro HATA
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Lens drive device, image-capturing device, and electronic apparatus with shape memory alloy actuator
Patent number: 8692929Abstract: An image-capturing device includes a detector which detects that a resistance value of an actuator, made of shape memory alloy, is maintained within a predetermined range. The image-capturing device moves a lens step by step from a place corresponding to a first field in order to obtain image data from each one of the fields provided in a focus region. The image-capturing device also calculates a target place, where the lens should be finally positioned, by using the obtained image data, and then positions the lens at the calculated target place. The foregoing structure allows obtaining reliable and stable data.Type: GrantFiled: March 5, 2010Date of Patent: April 8, 2014Assignee: Panasonic CorporationInventors: Kazuhiro Hata, Hirohiko Ina -
Patent number: 8692925Abstract: An optical system drive device, an image capture device, and a mobile device of the invention includes: an optical system; a urging member; a shape-memory alloy actuator; a current applying section for supplying a current to the actuator; a measurement section for measuring a characteristic value of the actuator; a driving control section for controlling the supply current to the current applying section according to the characteristic value measured by the measurement section; and a signal output section for outputting prescribed signal to the driving control section when the characteristic value of the actuator measured by the measurement section reaches a value corresponding to a target position of the optical system while making the shape-memory alloy of the actuator change the length at least in an extending mode when moving the optical system to the target position.Type: GrantFiled: January 13, 2011Date of Patent: April 8, 2014Assignee: Panasonic CorporationInventor: Kazuhiro Hata
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Publication number: 20120092547Abstract: An optical system drive device, an image capture device, and a mobile device of the invention includes: an optical system; a urging member; a shape-memory alloy actuator; a current applying section for supplying a current to the actuator; a measurement section for measuring a characteristic value of the actuator; a driving control section for controlling the supply current to the current applying section according to the characteristic value measured by the measurement section; and a signal output section for outputting prescribed signal to the driving control section when the characteristic value of the actuator measured by the measurement section reaches a value corresponding to a target position of the optical system while making the shape-memory alloy of the actuator change the length at least in an extending mode when moving the optical system to the target position.Type: ApplicationFiled: January 13, 2011Publication date: April 19, 2012Inventor: Kazuhiro Hata
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Publication number: 20110128434Abstract: An image-capturing device includes a detector which detects that a resistance value of an actuator, made of shape memory alloy, is maintained within a predetermined range. The image-capturing device moves a lens step by step from a place corresponding to a first field in order to obtain image data from each one of the fields provided in a focus region. The image-capturing device also calculates a target place, where the lens should be finally positioned, by using the obtained image data, and then positions the lens at the calculated target place. The foregoing structure allows obtaining reliable and stable data.Type: ApplicationFiled: March 5, 2010Publication date: June 2, 2011Applicant: Panasonic CorporationInventors: Kazuhiro Hata, Hirohiko Ina
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Patent number: 7687849Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: GrantFiled: May 29, 2008Date of Patent: March 30, 2010Assignee: Elpida Memory, Inc.Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Publication number: 20080237752Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: ApplicationFiled: May 29, 2008Publication date: October 2, 2008Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Patent number: 7417291Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: GrantFiled: April 18, 2007Date of Patent: August 26, 2008Assignee: Elpida Memory, Inc.Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Publication number: 20070187783Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: ApplicationFiled: April 18, 2007Publication date: August 16, 2007Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Patent number: 7256085Abstract: A manufacturing method of a semiconductor memory device comprising the steps of: forming plural trenches in stripes in a semiconductor substrate and filling each of the trenches with an element isolation insulating film to form element isolation regions; sequentially forming a tunnel insulating film and a charge-storable film so as to cover active regions between the element isolation regions; forming an interlayer insulating film on the charge-storable film; forming plural control gates on the interlayer insulating film in a direction orthogonal to a longitudinal direction of the trenches; among source formation regions and drain formation regions alternately provided between the plural control gates, etching the element isolation insulating film in the source formation regions, using as a mask a resist film having openings in the source formation regions, to expose surfaces of the trenches; and carrying out isotropic plasma ion implantation on the source formation regions to form source diffusion layers inType: GrantFiled: March 11, 2005Date of Patent: August 14, 2007Assignee: Sharp Kabushiki KaishaInventors: Kazuhiro Hata, Shinichi Sato, Yukiharu Akiyama
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Patent number: 7224034Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: GrantFiled: November 2, 2004Date of Patent: May 29, 2007Assignee: Elpida Memory, Inc.Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Publication number: 20050199946Abstract: A manufacturing method of a semiconductor memory device comprising the steps of: forming plural trenches in stripes in a semiconductor substrate and filling each of the trenches with an element isolation insulating film to form element isolation regions; sequentially forming a tunnel insulating film and a charge-storable film so as to cover active regions between the element isolation regions; forming an interlayer insulating film on the charge-storable film; forming plural control gates on the interlayer insulating film in a direction orthogonal to a longitudinal direction of the trenches; among source formation regions and drain formation regions alternately provided between the plural control gates, etching the element isolation insulating film in the source formation regions, using as a mask a resist film having openings in the source formation regions, to expose surfaces of the trenches; and carrying out isotropic plasma ion implantation on the source formation regions to form source diffusion layers inType: ApplicationFiled: March 11, 2005Publication date: September 15, 2005Applicant: SHARP KABUSHIKI KAISHAInventors: Kazuhiro Hata, Shinichi Sato, Yukiharu Akiyama
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Publication number: 20050087880Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: ApplicationFiled: November 2, 2004Publication date: April 28, 2005Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Patent number: 6828242Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: GrantFiled: August 20, 2002Date of Patent: December 7, 2004Assignees: Hitachi, Ltd., NEC Corporation, NEC Electronics CorporationInventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Publication number: 20030040183Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: ApplicationFiled: August 20, 2002Publication date: February 27, 2003Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Patent number: 6513120Abstract: A transmission device including an advanced security system is provided to specify an illegally operated device, inhibit the illegal operations, prevent from forgetting to unlock a log-in status by a maintenance operator, and set permitted user level for each command. The security system for a transmission device in a network is formed with plural transmission devices each including, at least, a port for a control terminal, which controls the transmission devices, when a cable disconnection is detected in a port of one transmission device, a log-in status is unlocked for the one transmission device or the other transmission devices through the port.Type: GrantFiled: November 17, 1998Date of Patent: January 28, 2003Assignee: Fujitsu LimitedInventors: Hiroshi Kanzawa, Kazuhiro Hata
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Publication number: 20020194507Abstract: A transmission device including an advanced security system is provided to specify an illegally operated device, inhibit the illegal operations, prevent from forgetting to unlock a log-in status by a maintenance operator, and set permitted user level for each command. The security system for a transmission device in a network is formed with plural transmission devices each including, at least, a port for a control terminal, which controls the transmission devices, when a cable disconnection is detected in a port of one transmission device, a log-in status is unlocked for the one transmission device or the other transmission devices through the port.Type: ApplicationFiled: November 17, 1998Publication date: December 19, 2002Inventors: HIROSHI KANZAWA, KAZUHIRO HATA