Patents by Inventor Kazuhiro Hata

Kazuhiro Hata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096330
    Abstract: A speech recognition device includes: an acquisition part, acquiring a speech signal; a speech feature amount calculation part, calculating a speech feature amount; a first speech recognition part, based on the speech feature amount, performing speech recognition using a learned first E2E model, attaching a first tag to a vocabulary portion of a specific class in text that is a recognition result, and outputting the same; a second speech recognition part, based on the speech feature amount, performing speech recognition using a learned second E2E model, attaching a second tag to a vocabulary portion of a specific class in a phoneme that is a recognition result, and outputting the same; a phoneme replacement part, replacing a vocabulary with the first tag with a phoneme with the second tag; and an output part, converting the phoneme with the second tag into text and outputting the same.
    Type: Application
    Filed: August 22, 2023
    Publication date: March 21, 2024
    Applicant: Honda Motor Co., Ltd.
    Inventors: Yui SUDO, Kazuhiro NAKADAI, Kazuya Hata
  • Publication number: 20240069826
    Abstract: Provided is a printing apparatus capable of communicating with an information processing apparatus which displays a remaining amount of a color material in the printing apparatus on a display region based on information sent from the printing apparatus. The printing apparatus receives an obtaining request to obtain information on the printing apparatus from the information processing apparatus, and controls a display color of the color material such that a color difference between the display color of the color material and a background color of the display region becomes more than or equal to a predetermined value. The printing apparatus sends information on the printing apparatus including the controlled display color and the remaining amount of the color material to the information processing apparatus as a response to the obtaining request.
    Type: Application
    Filed: July 14, 2023
    Publication date: February 29, 2024
    Inventor: Kazuhiro Hata
  • Patent number: 10123681
    Abstract: An endoscope insertion shape observation apparatus includes an endoscope, a magnetic field generation coil provided at an insertion portion of the endoscope and configured to generate a magnetic field, an antenna unit configured to receive a coil signal from the magnetic field generation coil, a bending portion configured to bend the insertion portion, a bending drive section configured to drive the bending portion to bend, an insertion shape processing circuit configured to generate an insertion shape of the endoscope inserted into a subject according to a signal received from the antenna unit, a touch panel configured to display a generation result of the insertion shape processing circuit and be able to perform touch operation, and a drive section control circuit configured to control a drive amount of the bending drive section based on the touch operation on a desired location of the insertion shape displayed on the touch panel.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: November 13, 2018
    Assignee: OLYMPUS CORPORATION
    Inventors: Keijiro Omoto, Takashi Yamashita, Kensuke Miyake, Kazuhiro Hata, Fumiyuki Onoda
  • Publication number: 20170055809
    Abstract: An endoscope insertion shape observation apparatus includes an endoscope, a magnetic field generation coil provided at an insertion portion of the endoscope and configured to generate a magnetic field, an antenna unit configured to receive a coil signal from the magnetic field generation coil, a bending portion configured to bend the insertion portion, a bending drive section configured to drive the bending portion to bend, an insertion shape processing circuit configured to generate an insertion shape of the endoscope inserted into a subject according to a signal received from the antenna unit, a touch panel configured to display a generation result of the insertion shape processing circuit and be able to perform touch operation, and a drive section control circuit configured to control a drive amount of the bending drive section based on the touch operation on a desired location of the insertion shape displayed on the touch panel.
    Type: Application
    Filed: November 16, 2016
    Publication date: March 2, 2017
    Applicant: OLYMPUS CORPORATION
    Inventors: Keijiro OMOTO, Takashi YAMASHITA, Kensuke MIYAKE, Kazuhiro HATA, Fumiyuki ONODA
  • Publication number: 20160331210
    Abstract: An insertion apparatus includes an insertion portion, a power spiral tube provided with a spiral fin portion configured to extend in a spiral shape, the power spiral tube being provided on an outer circumferential direction side of the insertion portion so as to be rotatable with respect to the insertion portion around a longitudinal axis, a first motor configured to generate a drive force to rotate the power spiral tube, an operation section provided on a proximal end side of the insertion portion, a second motor configured to generate a drive force to rotate the insertion portion pivotably held to the operation section, and a second motor drive circuit configured to calculate torque to be added to the power spiral tube and perform control so as to drive the second motor in accordance with torque added to the first motor.
    Type: Application
    Filed: July 27, 2016
    Publication date: November 17, 2016
    Applicant: OLYMPUS CORPORATION
    Inventors: Fumiyuki ONODA, Takashi YAMASHITA, Keijiro OMOTO, Kensuke MIYAKE, Kazuhiro HATA
  • Patent number: 8692929
    Abstract: An image-capturing device includes a detector which detects that a resistance value of an actuator, made of shape memory alloy, is maintained within a predetermined range. The image-capturing device moves a lens step by step from a place corresponding to a first field in order to obtain image data from each one of the fields provided in a focus region. The image-capturing device also calculates a target place, where the lens should be finally positioned, by using the obtained image data, and then positions the lens at the calculated target place. The foregoing structure allows obtaining reliable and stable data.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: April 8, 2014
    Assignee: Panasonic Corporation
    Inventors: Kazuhiro Hata, Hirohiko Ina
  • Patent number: 8692925
    Abstract: An optical system drive device, an image capture device, and a mobile device of the invention includes: an optical system; a urging member; a shape-memory alloy actuator; a current applying section for supplying a current to the actuator; a measurement section for measuring a characteristic value of the actuator; a driving control section for controlling the supply current to the current applying section according to the characteristic value measured by the measurement section; and a signal output section for outputting prescribed signal to the driving control section when the characteristic value of the actuator measured by the measurement section reaches a value corresponding to a target position of the optical system while making the shape-memory alloy of the actuator change the length at least in an extending mode when moving the optical system to the target position.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: April 8, 2014
    Assignee: Panasonic Corporation
    Inventor: Kazuhiro Hata
  • Publication number: 20120092547
    Abstract: An optical system drive device, an image capture device, and a mobile device of the invention includes: an optical system; a urging member; a shape-memory alloy actuator; a current applying section for supplying a current to the actuator; a measurement section for measuring a characteristic value of the actuator; a driving control section for controlling the supply current to the current applying section according to the characteristic value measured by the measurement section; and a signal output section for outputting prescribed signal to the driving control section when the characteristic value of the actuator measured by the measurement section reaches a value corresponding to a target position of the optical system while making the shape-memory alloy of the actuator change the length at least in an extending mode when moving the optical system to the target position.
    Type: Application
    Filed: January 13, 2011
    Publication date: April 19, 2012
    Inventor: Kazuhiro Hata
  • Publication number: 20110128434
    Abstract: An image-capturing device includes a detector which detects that a resistance value of an actuator, made of shape memory alloy, is maintained within a predetermined range. The image-capturing device moves a lens step by step from a place corresponding to a first field in order to obtain image data from each one of the fields provided in a focus region. The image-capturing device also calculates a target place, where the lens should be finally positioned, by using the obtained image data, and then positions the lens at the calculated target place. The foregoing structure allows obtaining reliable and stable data.
    Type: Application
    Filed: March 5, 2010
    Publication date: June 2, 2011
    Applicant: Panasonic Corporation
    Inventors: Kazuhiro Hata, Hirohiko Ina
  • Patent number: 7687849
    Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: March 30, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
  • Publication number: 20080237752
    Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.
    Type: Application
    Filed: May 29, 2008
    Publication date: October 2, 2008
    Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
  • Patent number: 7417291
    Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: August 26, 2008
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
  • Publication number: 20070187783
    Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.
    Type: Application
    Filed: April 18, 2007
    Publication date: August 16, 2007
    Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
  • Patent number: 7256085
    Abstract: A manufacturing method of a semiconductor memory device comprising the steps of: forming plural trenches in stripes in a semiconductor substrate and filling each of the trenches with an element isolation insulating film to form element isolation regions; sequentially forming a tunnel insulating film and a charge-storable film so as to cover active regions between the element isolation regions; forming an interlayer insulating film on the charge-storable film; forming plural control gates on the interlayer insulating film in a direction orthogonal to a longitudinal direction of the trenches; among source formation regions and drain formation regions alternately provided between the plural control gates, etching the element isolation insulating film in the source formation regions, using as a mask a resist film having openings in the source formation regions, to expose surfaces of the trenches; and carrying out isotropic plasma ion implantation on the source formation regions to form source diffusion layers in
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: August 14, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuhiro Hata, Shinichi Sato, Yukiharu Akiyama
  • Patent number: 7224034
    Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: May 29, 2007
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
  • Publication number: 20050199946
    Abstract: A manufacturing method of a semiconductor memory device comprising the steps of: forming plural trenches in stripes in a semiconductor substrate and filling each of the trenches with an element isolation insulating film to form element isolation regions; sequentially forming a tunnel insulating film and a charge-storable film so as to cover active regions between the element isolation regions; forming an interlayer insulating film on the charge-storable film; forming plural control gates on the interlayer insulating film in a direction orthogonal to a longitudinal direction of the trenches; among source formation regions and drain formation regions alternately provided between the plural control gates, etching the element isolation insulating film in the source formation regions, using as a mask a resist film having openings in the source formation regions, to expose surfaces of the trenches; and carrying out isotropic plasma ion implantation on the source formation regions to form source diffusion layers in
    Type: Application
    Filed: March 11, 2005
    Publication date: September 15, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kazuhiro Hata, Shinichi Sato, Yukiharu Akiyama
  • Publication number: 20050087880
    Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.
    Type: Application
    Filed: November 2, 2004
    Publication date: April 28, 2005
    Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
  • Patent number: 6828242
    Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: December 7, 2004
    Assignees: Hitachi, Ltd., NEC Corporation, NEC Electronics Corporation
    Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
  • Publication number: 20030040183
    Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.
    Type: Application
    Filed: August 20, 2002
    Publication date: February 27, 2003
    Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
  • Patent number: 6513120
    Abstract: A transmission device including an advanced security system is provided to specify an illegally operated device, inhibit the illegal operations, prevent from forgetting to unlock a log-in status by a maintenance operator, and set permitted user level for each command. The security system for a transmission device in a network is formed with plural transmission devices each including, at least, a port for a control terminal, which controls the transmission devices, when a cable disconnection is detected in a port of one transmission device, a log-in status is unlocked for the one transmission device or the other transmission devices through the port.
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: January 28, 2003
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Kanzawa, Kazuhiro Hata