Abstract: An image captured from a camera is subjected to distortion correction processing performed in real time with high accuracy at low cost and is rendered as a smooth image. The image captured from the camera via a capture circuit is stored in a frame memory of a rendering memory unit, and is then subjected to image correction processing by a rendering processing unit. The rendering processing unit adds control points to the image based on distortion information stored in a correction information storing unit, and performs processing so that a shape of a mesh region formed when the control points of the image are connected to one another becomes square by moving the control points. This processing is corrected using, for example, a bilinear filter and the like.

Abstract: An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.

Abstract: An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.

Abstract: An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.

Abstract: An image captured from a camera is subjected to distortion correction processing performed in real time with high accuracy at low cost and is rendered as a smooth image. The image captured from the camera via a capture circuit is stored in a frame memory of a rendering memory unit, and is then subjected to image correction processing by a rendering processing unit. The rendering processing unit adds control points to the image based on distortion information stored in a correction information storing unit, and performs processing so that a shape of a mesh region formed when the control points of the image are connected to one another becomes square by moving the control points. This processing is corrected using, for example, a bilinear filter and the like.

Abstract: An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.

Abstract: A semiconductor device is connected to a CPU, a memory and I/O devices to serve as a data transfer bridge for efficient data transfer between the memory and the I/O devices. A CPU interface and a plurality of I/O interfaces included in a bridge chip are connected through an internal bus to a memory interface included in the bridge chip. Each I/O interface has a read/write buffer and a DMAC. An arbiter included in the bridge chip determines a bus master for which data transfer is permitted in response to requests for data transfer from each of the CPU interface and the DMAC to the memory. Each of the I/O interfaces has a control function to skip part of areas in the memory when transferring data between the memory and the I/O interface.