Patents by Inventor Kazuhiro Imao

Kazuhiro Imao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8064028
    Abstract: A method for manufacturing an electro-optical device including an element substrate which includes a plurality of pixels including pixel electrodes and which is connected to a circuit board includes providing a UV-curable molding member on the element substrate such that the molding member extends from the element substrate to the circuit board and also includes curing the molding member by irradiating the molding member with UV light. The element substrate includes an electrostatic protection circuit. The electrostatic protection circuit is shielded from the UV light applied to the molding member in the operation of curing the molding member.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: November 22, 2011
    Assignee: Sony Corporation
    Inventors: Shigenori Katayama, Tomohide Onogi, Kazuhiro Imao
  • Patent number: 7439114
    Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: October 21, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi Kuwahara
  • Publication number: 20080225193
    Abstract: A method for manufacturing an electro-optical device including an element substrate which includes a plurality of pixels including pixel electrodes and which is connected to a circuit board includes providing a UV-curable molding member on the element substrate such that the molding member extends from the element substrate to the circuit board and also includes curing the molding member by irradiating the molding member with UV light. The element substrate includes an electrostatic protection circuit. The electrostatic protection circuit is shielded from the UV light applied to the molding member in the operation of curing the molding member.
    Type: Application
    Filed: December 10, 2007
    Publication date: September 18, 2008
    Applicant: EPSON IMAGING DEVICES CORPORATION
    Inventors: Shigenori KATAYAMA, Tomohide ONOGI, Kazuhiro IMAO
  • Patent number: 7061017
    Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: June 13, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi Kuwahara
  • Publication number: 20050287825
    Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.
    Type: Application
    Filed: August 18, 2005
    Publication date: December 29, 2005
    Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi kuwahara
  • Publication number: 20050225253
    Abstract: The invention is directed to reduction of a pattern size of a driving transistor of an emissive element and an improvement of an aperture ratio of a pixel. A second active layer of a driving TFT is formed of a two laminated polysilicon layers. The upper polysilicon layer is formed at the same time when a polysilicon layer forming a first active layer of a pixel selecting TFT is formed, and has a same thickness as that of the first active layer. Therefore, the second active layer is formed thicker by a film thickness of the lower polysilicon layer. An average crystal grain size of the second active layer is smaller than an average crystal grain size of the first active layer. Therefore, a carrier mobility of the driving TFT is lower than a carrier mobility of the pixel selecting TFT. This can shorten a channel length of the driving TFT.
    Type: Application
    Filed: April 7, 2005
    Publication date: October 13, 2005
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Tsutomu Yamada, Kazuhiro Imao
  • Publication number: 20050062047
    Abstract: A device has a first transistor and a second transistor wherein a channel length direction of the first transistor extends along a first direction and a channel length direction of the second transistor extends along a second direction intersecting the first direction, and the second transistor is formed on a same substrate as the first transistor. A first channel region and a second channel region are formed in semiconductor layers which are simultaneously formed and a mobility of the semiconductor film has an anisotropy in the first and second directions. With this structure, transistors having different mobilities can be obtained while using the semiconductor films formed on the same substrate and from a same material. For example, it is possible to form a transistor in which a high resistance is required using a semiconductor layer of the same characteristics as that in a transistor in which a high speed operation is desired, on the same substrate and with a minimum area.
    Type: Application
    Filed: September 21, 2004
    Publication date: March 24, 2005
    Inventors: Ryuji Nishikawa, Kazuhiro Imao, Ken Wakita, Kiyoshi Yoneda
  • Patent number: 6797651
    Abstract: A laser annealing apparatus is provided in which laser light is irradiated onto an amorphous semiconductor layer placed inside an annealing chamber through a chamber window, thereby poly-crystallizing the amorphous semiconductor film. Inside the annealing chamber a low degree vacuum (about 1.3×103 Pa to about 1.3 Pa) is maintained at a room temperature. An inert gas such as nitrogen, hydrogen, or argon is introduced into the atmosphere while maintaining the low degree vacuum. As a result, the surface smoothness of the polycrystalline semiconductor layer is comparable to that resulting from high degree vacuum annealing, while, unlike high degree vacuum annealing, there is less contamination of the chamber window and productivity is improved.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: September 28, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takashi Hagino, Kazuhiro Imao, Ken Wakita, Toshio Monzen, Hidenori Ogata, Shiro Nakanishi, Yoshihiro Morimoto
  • Publication number: 20040106246
    Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.
    Type: Application
    Filed: November 14, 2003
    Publication date: June 3, 2004
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi Kuwahara
  • Publication number: 20020142567
    Abstract: A laser annealing apparatus is provided in which laser light is irradiated onto an amorphous semiconductor layer placed inside an annealing chamber (100) through a chamber window (120), thereby poly-crystallizing the amorphous semiconductor film. Inside the annealing chamber 100 a low degree vacuum (about 1.3×103 Pa to about 1.3 Pa) is maintained at a room temperature. An inert gas such as nitrogen, hydrogen, or argon is introduced into the atmosphere while maintaining the low degree vacuum. As a result, the surface smoothness of the polycrystalline semiconductor layer is comparable to that resulting from high degree vacuum annealing, while, unlike high degree vacuum annealing, there is less contamination of the chamber window (120) and productivity is improved.
    Type: Application
    Filed: February 22, 2002
    Publication date: October 3, 2002
    Inventors: Takashi Hagino, Kazuhiro Imao, Ken Wakita, Toshio Monzen, Hidenori Ogata, Shiro Nakanishi, Yoshihiro Morimoto
  • Patent number: 6426791
    Abstract: Reflectance of a p-Si film crystallized by laser annealing is measured, a wave length dependency of the reflectance is found, and a first order rate of change is calculated to determine a minimum value near a wave length of 500 nm. The value is to be an inherent optical value under the laser power and relates to a grain size measured by Secco etching or the like. A number of correspondence between the optical value and the grain size are recorded and linearly plotted. By calculating the optical value from the reflectance in the p-Si film at in-line, the grain size is correspondingly determined. Thus, the semiconductor film can be in-line monitored, thereby improving a yield and saving a cost in producing a semiconductor device.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: July 30, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kazuhiro Imao, Takashi Kuwahara, Yoshihiro Morimoto, Kiyoshi Yoneda
  • Publication number: 20010017695
    Abstract: Reflectance of a p-Si film crystallized by laser annealing is measured, a wave length dependency of the reflectance is found, and a first order rate of change is calculated to determine a minimum value near a wave length of 500 nm. The value is to be an inherent optical value under the laser power and relates to a grain size measured by Secco etching or the like. A number of correspondence between the optical value and the grain size are recorded and linearly plotted. By calculating the optical value from the reflectance in the p-Si film at in-line, the grain size is correspondingly determined. Thus, the semiconductor film can be in-line monitored, thereby improving a yield and saving a cost in producing a semiconductor device.
    Type: Application
    Filed: February 22, 2001
    Publication date: August 30, 2001
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Kazuhiro Imao, Takashi Kuwahara, Yoshihiro Morimoto, Kiyoshi Yoneda
  • Patent number: 6274414
    Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: August 14, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi Kuwahara
  • Patent number: 6218198
    Abstract: Reflectance of a p-Si film crystallized by laser annealing is measured, a wavelength dependency of the reflectance is found, and a first order rate of change is calculated to determine a minimum value near a wavelength of 500 nm. The value is to be an inherent optical value under the laser power and relates to a grain size measured by Secco etching or the like. A number of correspondence between the optical value and the grain size are recorded and linearly plotted. By calculating the optical value from the reflectance in the p-Si film at in-line, the grain size is correspondingly determined. Thus, the semiconductor film can be in-line monitored, thereby improving a yield and saving a cost in producing a semiconductor device.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: April 17, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kazuhiro Imao, Takashi Kuwahara, Yoshihiro Morimoto, Kiyoshi Yoneda