Abstract: A semiconductor device of the present invention includes a booster circuit that boosts a selected word line (WL) to a given voltage higher than a power supply voltage and a charge pump circuit that retains the boosted word line (WL) at the first given voltage. When the booster circuit boosts the word line, the voltage level is degraded as the time goes. However, it is possible to program the memory cell and read out thereof properly by retaining the voltage of the word line with the charge pump circuit.

Abstract: A semiconductor device of the present invention includes a booster circuit that boosts a selected word line (WL) to a given voltage higher than a power supply voltage and a charge pump circuit that retains the boosted word line (WL) at the first given voltage. When the booster circuit boosts the word line, the voltage level is degraded as the time goes. However, it is possible to program the memory cell and read out thereof properly by retaining the voltage of the word line with the charge pump circuit.

Abstract: A semiconductor device of the present invention includes a booster circuit that boosts a selected word line (WL) to a given voltage higher than a power supply voltage and a charge pump circuit that retains the boosted word line (WL) at the first given voltage. When the booster circuit boosts the word line, the voltage level is degraded as the time goes. However, it is possible to program the memory cell and read out thereof properly by retaining the voltage of the word line with the charge pump circuit.

Abstract: A semiconductor memory device has a read ground and a write ground, these grounds being separately provided. Even when the read and verify operations are simultaneously executed, the source potential of an involved memory cell obtained at this time is equal to that obtained when either one of the read and verify operations is executed. Thus, the semiconductor memory device can perform the read operation at high speed with a sufficient operating margin regardless of whether the device is in the dual operation mode or not.

Abstract: A semiconductor device of the present invention includes a booster circuit that boosts a selected word line (WL) to a given voltage higher than a power supply voltage and a charge pump circuit that retains the boosted word line (WL) at the first given voltage. When the booster circuit boosts the word line, the voltage level is degraded as the time goes. However, it is possible to program the memory cell and read out thereof properly by retaining the voltage of the word line with the charge pump circuit.

Abstract: A semiconductor memory device has a read ground and a write ground, these grounds being separately provided. Even when the read and verify operations are simultaneously executed, the source potential of an involved memory cell obtained at this time is equal to that obtained when either one of the read and verify operations is executed. Thus, the semiconductor memory device can perform the read operation at high speed with a sufficient operating margin regardless of whether the device is in the dual operation mode or not.

Abstract: A semiconductor device of the present invention includes a booster circuit 20 that boosts a selected word line (WL) to a given voltage higher than a power supply voltage and a charge pump circuit that retains the boosted word line (WL) at the first given voltage. When the booster circuit boosts the word line, the voltage level is degraded as the time goes. However, it is possible to program the memory cell and read out thereof properly by retaining the voltage of the word line with the charge pump circuit.

Abstract: The present invention has an arrangement that includes a Y decoder that selects a main bit line MBL to which sub bit lines SBL connected to memory cells MC are connected and selects main bit lines MBL adjacent to the selected main bit line MBL, and a YRST transistor that connects the adjacent main bit lines MBL to a given interconnection line and set these main bit lines to a given voltage. With this structure, it is possible to restrain noise from the adjacent main bit lines MBL to the minimum and prevent degradation of the voltage margin.

Abstract: A semiconductor device includes a first terminal which receives a signal within a predetermined potential range in a first operation mode, and receives a potential higher above the predetermined potential range in a second operation mode, a high potential detection circuit which is connected to the first terminal, and detects the high potential to generate a high potential detection signal, a second terminal which receives a command signal, a latch circuit which latches the command signal supplied to the second terminal in response to the high potential detection signal, and a third terminal which resets the latch circuit in response to a signal within the predetermined potential range supplied from an exterior of the device.

Abstract: A memory device has an address terminal for inputting a plural bits of address signal, and a chip select terminal for inputting an external chip select signal, and an access mode controlling circuit which can switch a first control mode for controlling enable/disable of memory device according to plural external chip select signals and a predetermined address signal in the address signal to be input, and a second control mode for controlling the enable/disable according to a single external chip select signal. If the memory device is larger than a first memory area which can be controlled by a single chip select signal, the memory device can be directly connected to the memory control unit by setting the access mode control circuit to the first control mode. If the memory device is less than the first memory area, the access mode control circuit is set to the second control mode.

Abstract: A memory device has an address terminal for inputting a plural bits of address signal, and a chip select terminal for inputting an external chip select signal, and an access mode controlling circuit which can switch a first control mode for controlling enable/disable of memory device according to plural external chip select signals and a predetermined address signal in the address signal to be input, and a second control mode for controlling the enable/disable according to a single external chip select signal. If the memory device is larger than a first memory area which can be controlled by a single chip select signal, the memory device can be directly connected to the memory control unit by setting the access mode control circuit to the first control mode. If the memory device is less than the first memory area, the access mode control circuit is set to the second control mode.

Abstract: A semiconductor device includes a first terminal which receives a signal within a predetermined potential range in a first operation mode, and receives a potential higher above the predetermined potential range in a second operation mode, a high potential detection circuit which is connected to the first terminal, and detects the high potential to generate a high potential detection signal, a second terminal which receives a command signal, a latch circuit which latches the command signal supplied to the second terminal in response to the high potential detection signal, and a third terminal which resets the latch circuit in response to a signal within the predetermined potential range supplied from an exterior of the device.

Abstract: A non-volatile semiconductor memory includes a plurality of memory areas, a control unit which performs a data-write or data-erase operation with respect to one of the memory areas, an address-detection unit which detects an address that indicates the one of the memory areas having the data-write or data-erase operation performed therein, and supplies information indicative of the address, and at least one output terminal which supplies the information to an exterior of the device.

Abstract: The present invention provides a semiconductor nonvolatile memory provided with a plurality of memory cells having floating gates, which enables an optimum erase operation, even when the erase rate fluctuates due to production irregularities, by monitoring the state of a memory cell during erase process and controlling the erase voltage applied to a control gate in accordance with the state of erase progress. As a specific example of the state of a memory cell, which is monitored during erase process, leakage current of a memory cell during erase process is monitored.

Abstract: The present invention comprises a flash memory or similar nonvolatile memory circuit characterized by a constitution that enables read operations in two modes, a clock-synchronous burst read mode and a clock-asynchronous normal read mode, the device being set to normal read mode in response to power on, and being set to burst read mode in response to a control signal instructing the burst read mode. The memory device includes a burst mode switching circuit internally. This burst mode switching circuit sets an output circuit to normal read mode in response to the power ON so as to enable read operations not synchronized with the clock after the power ON. In response to a burst mode control signal provided by the system, the burst mode switching circuit sets the output circuit to burst read mode. Thus, the system can perform the burst read to the nonvolatile memory device under the environment analogous to conventional main memory access.