Patents by Inventor Kazuhiro Koshio

Kazuhiro Koshio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10476454
    Abstract: A power amplifier module includes a first current source that outputs a first current corresponding to a level control voltage for controlling a signal level of an amplified signal, a second current source that outputs a second current corresponding to the level control voltage, a first transistor in which an input signal and a first bias current are supplied to a base and an emitter is grounded, a second transistor in which an emitter is connected to a collector of the first transistor, the second current is supplied to a base, and a first amplified signal obtained by amplifying the input signal is output from a collector, and a third transistor in which the first current is supplied to a collector, a bias control current or voltage is supplied to a base, and the first bias current is supplied from an emitter to the base of the first transistor.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: November 12, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shota Ishihara, Seiko Ono, Yusuke Shimamune, Fuminori Morisawa, Shizuki Nakajima, Yuri Honda, Kazuhiro Koshio, Masato Sato
  • Publication number: 20190181816
    Abstract: A power amplifier module includes a first current source that outputs a first current corresponding to a level control voltage for controlling a signal level of an amplified signal, a second current source that outputs a second current corresponding to the level control voltage, a first transistor in which an input signal and a first bias current are supplied to a base and an emitter is grounded, a second transistor in which an emitter is connected to a collector of the first transistor, the second current is supplied to a base, and a first amplified signal obtained by amplifying the input signal is output from a collector, and a third transistor in which the first current is supplied to a collector, a bias control current or voltage is supplied to a base, and the first bias current is supplied from an emitter to the base of the first transistor.
    Type: Application
    Filed: February 20, 2019
    Publication date: June 13, 2019
    Inventors: Shota ISHIHARA, Seiko ONO, Yusuke SHIMAMUNE, Fuminori MORISAWA, Shizuki NAKAJIMA, Yuri HONDA, Kazuhiro KOSHIO, Masato SATO
  • Patent number: 10256778
    Abstract: A power amplifier module includes a first current source that outputs a first current corresponding to a level control voltage for controlling a signal level of an amplified signal, a second current source that outputs a second current corresponding to the level control voltage, a first transistor in which an input signal and a first bias current are supplied to a base and an emitter is grounded, a second transistor in which an emitter is connected to a collector of the first transistor, the second current is supplied to a base, and a first amplified signal obtained by amplifying the input signal is output from a collector, and a third transistor in which the first current is supplied to a collector, a bias control current or voltage is supplied to a base, and the first bias current is supplied from an emitter to the base of the first transistor.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 9, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shota Ishihara, Seiko Ono, Yusuke Shimamune, Fuminori Morisawa, Shizuki Nakajima, Yuri Honda, Kazuhiro Koshio, Masato Sato
  • Publication number: 20180302045
    Abstract: A power amplifier module includes a first current source that outputs a first current corresponding to a level control voltage for controlling a signal level of an amplified signal, a second current source that outputs a second current corresponding to the level control voltage, a first transistor in which an input signal and a first bias current are supplied to a base and an emitter is grounded, a second transistor in which an emitter is connected to a collector of the first transistor, the second current is supplied to a base, and a first amplified signal obtained by amplifying the input signal is output from a collector, and a third transistor in which the first current is supplied to a collector, a bias control current or voltage is supplied to a base, and the first bias current is supplied from an emitter to the base of the first transistor.
    Type: Application
    Filed: June 20, 2018
    Publication date: October 18, 2018
    Inventors: Shota ISHIHARA, Seiko ONO, Yusuke SHIMAMUNE, Fuminori MORISAWA, Shizuki NAKAJIMA, Yuri HONDA, Kazuhiro KOSHIO, Masato SATO
  • Patent number: 10044330
    Abstract: A power amplifier module includes a first current source that outputs a first current corresponding to a level control voltage for controlling a signal level of an amplified signal, a second current source that outputs a second current corresponding to the level control voltage, a first transistor in which an input signal and a first bias current are supplied to a base and an emitter is grounded, a second transistor in which an emitter is connected to a collector of the first transistor, the second current is supplied to a base, and a first amplified signal obtained by amplifying the input signal is output from a collector, and a third transistor in which the first current is supplied to a collector, a bias control current or voltage is supplied to a base, and the first bias current is supplied from an emitter to the base of the first transistor.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: August 7, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shota Ishihara, Seiko Ono, Yusuke Shimamune, Fuminori Morisawa, Shizuki Nakajima, Yuri Honda, Kazuhiro Koshio, Masato Sato
  • Publication number: 20180083581
    Abstract: A power amplifier module includes a first current source that outputs a first current corresponding to a level control voltage for controlling a signal level of an amplified signal, a second current source that outputs a second current corresponding to the level control voltage, a first transistor in which an input signal and a first bias current are supplied to a base and an emitter is grounded, a second transistor in which an emitter is connected to a collector of the first transistor, the second current is supplied to a base, and a first amplified signal obtained by amplifying the input signal is output from a collector, and a third transistor in which the first current is supplied to a collector, a bias control current or voltage is supplied to a base, and the first bias current is supplied from an emitter to the base of the first transistor.
    Type: Application
    Filed: September 20, 2017
    Publication date: March 22, 2018
    Inventors: Shota ISHIHARA, Seiko ONO, Yusuke SHIMAMUNE, Fuminori MORISAWA, Shizuki NAKAJIMA, Yuri HONDA, Kazuhiro KOSHIO, Masato SATO
  • Patent number: 7994860
    Abstract: An electronic component for high frequency power amplification realizes an improvement in switching spectrum characteristics. The gain of an amplifying NMOS transistor is controlled by a bias voltage on which a bias control voltage is reflected. Further, a threshold voltage compensator compensates for a variation in threshold voltage with variations in the manufacture of the amplifying NMOS transistor. The threshold voltage compensator includes an NMOS transistor formed in the same process specification as the amplifying NMOS transistor and converts a variation in current flowing through the NMOS transistor depending on the variation in the threshold voltage of the amplifying NMOS transistor to its corresponding voltage by a resistor to compensate for the bias voltage. It is thus possible to reduce variations in so-called precharge level brought to fixed output power in a region (0 dBm or less, for example) low in output power.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: August 9, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kyoichi Takahashi, Kazuhiro Koshio, Satoshi Tanaka
  • Publication number: 20100102887
    Abstract: An electronic component for high frequency power amplification realizes an improvement in switching spectrum characteristics. The gain of an amplifying NMOS transistor is controlled by a bias voltage on which a bias control voltage is reflected. Further, a threshold voltage compensator compensates for a variation in threshold voltage with variations in the manufacture of the amplifying NMOS transistor. The threshold voltage compensator includes an NMOS transistor formed in the same process specification as the amplifying NMOS transistor and converts a variation in current flowing through the NMOS transistor depending on the variation in the threshold voltage of the amplifying NMOS transistor to its corresponding voltage by a resistor to compensate for the bias voltage. It is thus possible to reduce variations in so-called precharge level brought to fixed output power in a region (0 dBm or less, for example) low in output power.
    Type: Application
    Filed: September 24, 2009
    Publication date: April 29, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Kyoichi TAKAHASHI, Kazuhiro KOSHIO, Satoshi TANAKA
  • Patent number: 7395036
    Abstract: In a high frequency power amplifier circuit in which bias voltages are applied to the transistors for amplification by current mirroring, The power amplifier includes a detection circuit including a transistor for detection which receives the AC component of an input signal to the last-stage transistor for amplification at its control terminal, a current mirror circuit which mirrors current flowing through that transistor, and a current-voltage converter which converts current flowing in the slave side of the current mirror circuit into a voltage. In the detection circuit, a voltage from a bias circuit for generating the bias voltages for the transistors for amplification is applied to the control terminal of the transistor for detections, and output of the detection circuit is applied to the control terminal of the last-stage transistor for amplification.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: July 1, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Hitoshi Akamine, Masahiro Tsuchiya, Kyoichi Takahashi, Kazuhiro Koshio
  • Patent number: 7271662
    Abstract: In a high frequency power amplifier circuit in which bias voltages are applied to the transistors for amplification by current mirroring, this invention enables preventing waveform distortion near the peak output power level by allowing sufficient idle currents to flow through the transistors for amplification, while enhancing the power efficiency in a low output power region. The power amplifier includes a detection circuit comprising a transistor for detection which receives the AC component of an input signal to the last-stage transistor for amplification at its control terminal, a current mirror circuit which mirrors current flowing through that transistor, and a current-voltage conversion means which converts current flowing in the slave side of the current mirror circuit into a voltage.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: September 18, 2007
    Assignee: Renesas Technology Corporation
    Inventors: Hitoshi Akamine, Masahiro Tsuchiya, Kyoichi Takahashi, Kazuhiro Koshio
  • Patent number: 7271658
    Abstract: An RF power module in which operating voltage is controlled by a control signal based on amplitude information includes a temperature detecting device which is provided over a semiconductor chip formed with an amplifying transistor or a semiconductor chip formed with a power source circuit; and a detector having a hysteresis characteristic which is provided over the semiconductor chip formed with the device or a different semiconductor chip, applies a bias to the temperature detecting device to compare the state of the device at two reference levels, outputs a signal indicating abnormality when judging that the temperature of the semiconductor chip formed with the temperature detecting device is above a predetermined temperature, and outputs a signal indicating normality when judging that the temperature of the semiconductor chip is below a second predetermined temperature lower than the predetermined temperature.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: September 18, 2007
    Assignees: Renesas Technology Corp., Hitachi Hybrid Network, Co., Ltd.
    Inventors: Kouichi Matsushita, Kenichi Shimamoto, Kazuhiro Koshio, Kazuhiko Ishimoto, Takayuki Tsutsui
  • Publication number: 20060066404
    Abstract: In a high frequency power amplifier circuit in which bias voltages are applied to the transistors for amplification by current mirroring, The power amplifier includes a detection circuit including a transistor for detection which receives the AC component of an input signal to the last-stage transistor for amplification at its control terminal, a current mirror circuit which mirrors current flowing through that transistor, and a current-voltage converter which converts current flowing in the slave side of the current mirror circuit into a voltage. In the detection circuit, a voltage from a bias circuit for generating the bias voltages for the transistors for amplification is applied to the control terminal of the transistor for detection, and output of the detection circuit is applied to the control terminal of the last-stage transistor for amplification.
    Type: Application
    Filed: September 1, 2005
    Publication date: March 30, 2006
    Inventors: Hitoshi Akamine, Masahiro Tsuchiya, Kyoichi Takahashi, Kazuhiro Koshio
  • Publication number: 20060066398
    Abstract: In a high frequency power amplifier circuit in which bias voltages are applied to the transistors for amplification by current mirroring, this invention enables preventing waveform distortion near the peak output power level by allowing sufficient idle currents to flow through the transistors for amplification, while enhancing the power efficiency in a low output power region. The power amplifier includes a detection circuit comprising a transistor for detection which receives the AC component of an input signal to the last-stage transistor for amplification at its control terminal, a current mirror circuit which mirrors current flowing through that transistor, and a current-voltage conversion means which converts current flowing in the slave side of the current mirror circuit into a voltage.
    Type: Application
    Filed: September 16, 2005
    Publication date: March 30, 2006
    Inventors: Hitoshi Akamine, Masahiro Tsuchiya, Kyoichi Takahashi, Kazuhiro Koshio
  • Publication number: 20050280471
    Abstract: An RF power module in which operating voltage is controlled by a control signal based on amplitude information includes a temperature detecting device which is provided over a semiconductor chip formed with an amplifying transistor or a semiconductor chip formed with a power source circuit; and a detector having a hysteresis characteristic which is provided over the semiconductor chip formed with the device or a different semiconductor chip, applies a bias to the temperature detecting device to compare the state of the device at two reference levels, outputs a signal indicating abnormality when judging that the temperature of the semiconductor chip formed with the temperature detecting device is above a predetermined temperature, and outputs a signal indicating normality when judging that the temperature of the semiconductor chip is below a second predetermined temperature lower than the predetermined temperature.
    Type: Application
    Filed: June 10, 2005
    Publication date: December 22, 2005
    Inventors: Kouichi Matsushita, Kenichi Shimamoto, Kazuhiro Koshio, Kazuhiko Ishimoto, Takayuki Tsutsui
  • Patent number: 5805214
    Abstract: Image data photographed by a video camera 20 are compressed by a compression and decompression circuit 5, the compressed image data are recorded in an incorporated type semiconductor memory 6 or disk-type memory 13 fixed in the video camera 20 and the recorded image data are transferred to an external recording device 23. Further, the external recording device 23 records the transferred image data in a data storage while they are being compressed. The video camera 20 receives, decompresses and converts into a television signal the compressed image data read by the external recording device 23 in reproducing them. A video camera system capable of recording and reproducing long hours of image data by using a video camera having an ultra small size comparable to that of an 8 mm video cassette can be realized by using such a construction.
    Type: Grant
    Filed: April 1, 1997
    Date of Patent: September 8, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Akihito Nishizawa, Takuya Imaide, Toshiro Kinugasa, Takuya Iguchi, Kazuhiro Koshio
  • Patent number: 5646684
    Abstract: Image data photographed by a video camera 20 is compressed by a compression and decompression circuit 5, the compressed image data is recorded in an incorporated type semiconductor memory 6 or disk-type memory 13 fixed in the video camera 20 and the recorded image data is transferred to an external recording device 23. Further, the external recording device 23 records the transferred image data in a data storage while it is being compressed. The video camera 20 receives, decompresses and converts into a television signal the compressed image data read by the external recording device 23 in a reproducing operation. A video camera system capable of recording and reproducing long hours of image data by using a video camera having an ultra small size comparable to that of an 8 mm video cassette can be realized by using such a construction.
    Type: Grant
    Filed: August 8, 1995
    Date of Patent: July 8, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Akihito Nishizawa, Takuya Imaide, Toshiro Kinugasa, Takuya Iguchi, Kazuhiro Koshio
  • Patent number: 5483290
    Abstract: A video camera in which an output signal from a solid-state image sensor is converted into the corresponding digital signal at the horizontal reading cycle of the output signal, and the digital signal is digital-processed with a first predetermined clock (fs) synchronous with the reading cycle to provide a luminance signal and a color difference signal.
    Type: Grant
    Filed: October 6, 1993
    Date of Patent: January 9, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyasu Ohtsubo, Kazuhiro Koshio
  • Patent number: 5287171
    Abstract: A video camera in which an output signal from a solid-state image sensor is converted into a corresponding digital signal at a horizontal reading cycle of the output signal, and the digital signal is digital-processed with a first predetermined clock (fs) synchronous with the reading cycle to provide a luminance signal and a color difference signal.
    Type: Grant
    Filed: October 29, 1991
    Date of Patent: February 15, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyasu Ohtsubo, Kazuhiro Koshio