Abstract: A computation apparatus, comprises a first processing unit configured to obtain a first feature by executing computation of a neural network with use of a first coefficient that is not to be updated in online learning of the neural network, a second processing unit configured to obtain a second feature by executing the computation of the neural network with use of the first feature and a second coefficient that is to be updated in the online learning, and an update unit configured to update the second coefficient by executing the online learning with use of the second coefficient and a second feature that has been obtained by the second processing unit in a past. Processing of the first processing unit and processing of the update unit are executed in parallel.

Abstract: An event processing method of a processor according to one or more embodiments may include detecting an event input, which notifies an occurrence of an event, detecting a wait event by an event input, changing a status from an execution status to a wait status and outputs a count start signal by an event wait instruction, and changes a status from the wait status to the execution status and outputs a count end signal by the detection of the wait event, incrementing a counter value from an initial value by output of the count start signal, and ends counting by output of the count end signal; and receiving and storing a count value of the timer counter by output of the count end signal.

Abstract: A pipeline processing unit includes a fetch unit that fetches the instruction for the thread having an execution right, a decoding unit that decodes the instruction fetched by the fetch unit, and a computation execution unit that executes the instruction decoded by the decoding unit. When the WAIT instruction for the thread having the execution right is executed, an instruction holding unit holds instruction fetch information on a processing target instruction to be processed immediately after the WAIT instruction. An execution target thread selection unit selects a thread to be executed based on a wait command and, in response to a wait state started from the execution of the WAIT instruction being canceled, processes the processing target instruction from decoding thereof based on the instruction fetch information on the processing target instruction held in the instruction holding unit.

Abstract: An event processing method of a processor according to one or more embodiments may include detecting an event input, which notifies an occurrence of an event, detecting a wait event by an event input, changing a status from an execution status to a wait status and outputs a count start signal by an event wait instruction, and changes a status from the wait status to the execution status and outputs a count end signal by the detection of the wait event, incrementing a counter value from an initial value by output of the count start signal, and ends counting by output of the count end signal; and receiving and storing a count value of the timer counter by output of the count end signal.

Abstract: Provided is a manipulator including: a link; a joint unit configured to rotate the link; and a distance sensor configured to detect an obstacle entering in a monitoring space that is determined so as to include at least a rotating direction side of the link, the distance sensor being installed so that a sensing direction faces a direction parallel to a surface of the link. Further, provided is a moving robot including the aforementioned manipulator.

Abstract: A program writing method in which a program is written into a flash ROM that a microcomputer includes therein includes: a generating step for generating a version representative value indicating a version of a source directory from predetermined types of files included in the source directory; an additionally writing step for additionally writing the version representative value into a source file included in the source directory; and a program writing step for writing a program corresponding to the source directory generated by compiling the source file into which the version representative value has been additionally written into the flash ROM.

Abstract: A posture angle calculation apparatus 170 includes an acquisition unit 171 configured to acquire an output of an acceleration sensor 151 installed to output acceleration of a moving apparatus that moves along a moving surface in a vertical axis direction with respect to the moving surface and to acquire an output of a gyro sensor 152 installed to output an angular velocity about the vertical axis. The posture angle calculation apparatus 170 further includes a calculation unit 172 configured to assume, when the acceleration is larger than reference acceleration Rg, and the angular velocity is smaller than a preset reference angular velocity Rw, the angular velocity ?z is zero and calculate a posture angle of the moving apparatus about the vertical axis. The posture angle calculation apparatus 170 further includes an output unit 173 configured to output data of the calculated posture angle.

Abstract: A pipeline processing unit includes a fetch unit that fetches the instruction for the thread having an execution right, a decoding unit that decodes the instruction fetched by the fetch unit, and a computation execution unit that executes the instruction decoded by the decoding unit. When the WAIT instruction for the thread having the execution right is executed, an instruction holding unit holds instruction fetch information on a processing target instruction to be processed immediately after the WAIT instruction. An execution target thread selection unit selects a thread to be executed based on a wait command and, in response to a wait state started from the execution of the WAIT instruction being canceled, processes the processing target instruction from decoding thereof based on the instruction fetch information on the processing target instruction held in the instruction holding unit.

Abstract: Provided is a storage device including: a first storage region comprising a plurality of sensor regions for the plurality of the sensors; a second storage region into which a data set is written, the data set being generated by reading, from the respective plurality of sensor regions, sampling data of a sensor having a longest sampling period among the plurality of sensors for one period and sampling data of other sensors for a period corresponding to the period in which the sampling data of the sensor for the one period is generated and integrating the sampling data; and a control unit configured to write the sampling data of the plurality of sensors into the plurality of sensor regions, respectively, in a ring buffer format and generate the data set at a predetermined timing and write the data set into the second storage region in the ring buffer format.

Abstract: A processor is disclosed that performs pipelining which processes a plurality of threads and executes instructions in concurrent processing, the instructions corresponding to thread numbers of the threads and including a branch instruction. The processor may include a pipeline processor, which includes a fetch part that fetches the instruction of the thread having an execution right, and a computation execution part that executes the instruction fetched by the fetch part. The processor may include a branch controller that determines whether to drop an instruction subsequent to the branch instruction within the pipeline processor based on the thread number of the thread where the branch instruction is executed and on the thread number of the subsequent instruction.

Abstract: A microcontroller unit includes: a first arithmetic processing unit, which is able to access a data bus; a second arithmetic processing unit, which includes a processor capable of accessing the data bus, and a memory. The microcontroller unit performs a data transmitting process between peripheral circuits connected to the data bus; a first arbitration circuit, which is embedded in the second arithmetic processing unit and arbitrates access to the data bus; and a second arbitration circuit, which is embedded in the second arithmetic processing unit and arbitrates access to the memory. The memory stores arithmetic processing sequences in association with event signals transmitted from the peripheral circuits, and in response to input of the event signals, the processor executes the arithmetic processing sequences corresponding to the event signals.

Abstract: Provided is a manipulator including: a link; a joint unit configured to rotate the link; and a distance sensor configured to detect an obstacle entering in a monitoring space that is determined so as to include at least a rotating direction side of the link, the distance sensor being installed so that a sensing direction faces a direction parallel to a surface of the link. Further, provided is a moving robot including the aforementioned manipulator.

Abstract: A posture angle calculation apparatus 170 includes an acquisition unit 171 configured to acquire an output of an acceleration sensor 151 installed to output acceleration of a moving apparatus that moves along a moving surface in a vertical axis direction with respect to the moving surface and to acquire an output of a gyro sensor 152 installed to output an angular velocity about the vertical axis. The posture angle calculation apparatus 170 further includes a calculation unit 172 configured to assume, when the acceleration is larger than reference acceleration Rg, and the angular velocity is smaller than a preset reference angular velocity Rw, the angular velocity ?z is zero and calculate a posture angle of the moving apparatus about the vertical axis. The posture angle calculation apparatus 170 further includes an output unit 173 configured to output data of the calculated posture angle.

Abstract: A processor is disclosed that performs pipelining which processes a plurality of threads and executes instructions in concurrent processing, the instructions corresponding to thread numbers of the threads and including a branch instruction. The processor may include a pipeline processor, which includes a fetch part that fetches the instruction of the thread having an execution right, and a computation execution part that executes the instruction fetched by the fetch part. The processor may include a branch controller that determines whether to drop an instruction subsequent to the branch instruction within the pipeline processor based on the thread number of the thread where the branch instruction is executed and on the thread number of the subsequent instruction.

Abstract: An arithmetic processor of an embodiment comprises program counter, a program memory, registers, and a decoder. Also the arithmetic processor comprises an arithmetic unit that carries out an operation using the operand and operator acquired from the registers based on a decode result by the decoder, a data memory that stores constant data and an address in association with the data, and a load unit that comprises a load data address storing unit that stores a load data address indicating an address where the constant data is stored; and an increment unit that updates the load data address stored in the load data address storing unit. The load unit loads, from the data memory, constant data corresponding to an address specified by an operand of a load instruction from the decoder, and stores the constant data in a specific one of the registers.

Abstract: Provided is a storage device including: a first storage region comprising a plurality of sensor regions for the plurality of the sensors; a second storage region into which a data set is written, the data set being generated by reading, from the respective plurality of sensor regions, sampling data of a sensor having a longest sampling period among the plurality of sensors for one period and sampling data of other sensors for a period corresponding to the period in which the sampling data of the sensor for the one period is generated and integrating the sampling data; and a control unit configured to write the sampling data of the plurality of sensors into the plurality of sensor regions, respectively, in a ring buffer format and generate the data set at a predetermined timing and write the data set into the second storage region in the ring buffer format.

Abstract: A program writing method in which a program is written into a flash ROM that a microcomputer includes therein includes: a generating step for generating a version representative value indicating a version of a source directory from predetermined types of files included in the source directory; an additionally writing step for additionally writing the version representative value into a source file included in the source directory; and a program writing step for writing a program corresponding to the source directory generated by compiling the source file into which the version representative value has been additionally written into the flash ROM.

Abstract: An arithmetic processing method is provided using a binary fixed-point arithmetic processing circuit to carry out an operation of multiplicatively dividing a dividend by a divisor. The method comprises shifting the divisor by a specific number of bits when the absolute value of the divisor is within a specific range, and holding the divisor without shifting the divisor when the absolute value of the divisor is out of the specific range, acquiring an initial value of approximation calculation for the divisor that is shifted or held without being shifted, calculating a reciprocal of the divisor by performing asymptotic approximation of the acquired initial value more than once, and calculating a product of the calculated reciprocal and the dividend, and shifting the calculated product by the specific number of bits when the divisor is shifted.

Abstract: A PWM signal generator includes a delay circuit unit, which includes a plurality of delay elements connected in series, an output terminal of the delay element in a final stage among the plurality of delay elements and an input terminal of the delay element in an initial stage among the plurality of delay elements being connected to each other; a selector, which selects any one of output signals of the plurality of delay elements based on a digital value; a PWM signal output unit, which outputs a PWM signal based on the output signal selected by the selector; a delay-amount detector, which detects an amount of delay of a signal due to the delay circuit unit; and a digital value generator, which generates the digital value by correcting predetermined data based on the amount of delay detected by the delay-amount detector.

Abstract: A PWM signal generator includes a delay circuit unit, which includes a plurality of delay elements connected in series, an output terminal of the delay element in a final stage among the plurality of delay elements and an input terminal of the delay element in an initial stage among the plurality of delay elements being connected to each other; a selector, which selects any one of output signals of the plurality of delay elements based on a digital value; a PWM signal output unit, which outputs a PWM signal based on the output signal selected by the selector; a delay-amount detector, which detects an amount of delay of a signal due to the delay circuit unit; and a digital value generator, which generate the digital value by correcting predetermined data based on the amount of delay detected by the delay-amount detector.