Abstract: A signal processing device according to an example embodiment includes: a distortion compensation circuit configured to execute distortion compensation processing of compensating for nonlinear distortion on an input signal, and output a signal subjected to the distortion compensation processing; an amplifier configured to amplify the signal output from the distortion compensation circuit and output the amplified signal as a communication signal; and a signal output circuit configured to output an adjustment signal for adjusting the distortion compensation processing to the distortion compensation circuit as the input signal at a timing at which the communication signal is not output, the adjustment signal having a frequency band that covers a frequency band of the communication signal.

Abstract: In one embodiment, a problem to be addressed by the present invention is to provide a novel cellular immunotherapy having a treatment and/or prevention effect against a tumor. In one embodiment, the present invention relates to a composition for use in treatment and/or prevention of a tumor in a subject comprising allogeneic CD4+ T cells, wherein the allogeneic CD4+ T cells have (a) MHC class II molecules all or part of which are different from MHC class II molecules of the subject, and contain (b) cells activated by ex vivo coculture with antigen-presenting cells derived from the subject or an individual having MHC class II molecules wholly identical or partially identical with the MHC class II molecules of the subject.

Abstract: A semiconductor device that includes a SiC semiconductor substrate; a SiC epitaxial layer having an impurity concentration lower than that of the SiC semiconductor substrate; a first semiconductor layer including first semiconductor pillars and second semiconductor pillars; a second semiconductor layer; a device active region; a termination region; a channel stopper region having an impurity concentration higher than that of the SiC epitaxial layer; and a plurality of first chip end portions and a plurality of second chip end portions, and a surface of the first side surface is covered with an impurity region having an impurity concentration higher than those of the first semiconductor pillar and the SiC epitaxial layer and is connected to the channel stopper region.

Abstract: A semiconductor device that includes a SiC semiconductor substrate; a SiC epitaxial layer having an impurity concentration lower than that of the SiC semiconductor substrate; a first semiconductor layer including first semiconductor pillars and second semiconductor pillars; a second semiconductor layer; a device active region; a termination region; a channel stopper region having an impurity concentration higher than that of the SiC epitaxial layer; and a plurality of first chip end portions and a plurality of second chip end portions, and a surface of the first side surface is covered with an impurity region having an impurity concentration higher than those of the first semiconductor pillar and the SiC epitaxial layer and is connected to the channel stopper region.

Abstract: A manufacturing yield and reliability of a semiconductor device including a power semiconductor element is improved. A plurality of trenches DT extending in an x direction and spaced apart from each other in a y direction orthogonal to the x direction are formed in a substrate having a main crystal surface tilted with respect to a <11-20> direction. Also, a super-junction structure is constituted of a p-type column region PC made of a semiconductor layer embedded in the trench DT and an n-type column region NC made of a part of the substrate between the trenches DT adjacent in the y direction, and an angle error between the extending direction of the trench DT (x direction) and the <11-20> direction is within ±?. The ? is determined by {arctan {k× (w/h)}}/13 for the trench having a height of h and a width of w. Herein, the k is at least smaller than 2, preferably 0.9 or less, more preferably 0.5 or less, and still more preferably 0.3 or less.

Abstract: A manufacturing yield and reliability of a semiconductor device including a power semiconductor element is improved. A plurality of trenches DT extending in an x direction and spaced apart from each other in a y direction orthogonal to the x direction are formed in a substrate having a main crystal surface tilted with respect to a <11-20> direction. Also, a super-junction structure is constituted of a p-type column region PC made of a semiconductor layer embedded in the trench DT and an n-type column region NC made of a part of the substrate between the trenches DT adjacent in the y direction, and an angle error between the extending direction of the trench DT (x direction) and the <11-20> direction is within ±?. The ? is determined by {arctan {k× (w/h)}}/13 for the trench having a height of h and a width of w. Herein, the k is at least smaller than 2, preferably 0.9 or less, more preferably 0.5 or less, and still more preferably 0.3 or less.

Abstract: In a silicon carbide semiconductor device, an n-type drift layer is formed on a front surface of an n++-type semiconductor substrate. Next, a trench is formed in the n-type drift layer, from a surface of the n-type drift layer. Next, a p-type pillar region is formed in the trench. A depth of the trench is at least three times a width of the trench. The p-type pillar region is formed by concurrently introducing a p-type first dopant and a gas containing an n-type second dopant incorporated at an atom position different from that of the first dopant.

Abstract: In a silicon carbide semiconductor device, an n-type drift layer is formed on a front surface of an n++-type semiconductor substrate. Next, a trench is formed in the n-type drift layer, from a surface of the n-type drift layer. Next, a p-type pillar region is formed in the trench. A depth of the trench is at least three times a width of the trench. The p-type pillar region is formed by concurrently introducing a p-type first dopant and a gas containing an n-type second dopant incorporated at an atom position different from that of the first dopant.

Abstract: A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm?3 or higher and 6×1017 cm?3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm?3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm?3 or higher and 8×1017 cm?3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm?3 or lower in a case of a junction barrier Schottky diode.

Abstract: In a semiconductor device having a silicon carbide device, a technique capable of suppressing variation in a breakdown voltage and achieving reduction in an area of a termination structure is provided. In order to solve the above-described problem, in the present invention, in a semiconductor device having a silicon carbide device, a p-type first region and a p-type second region provided to be closer to an outer peripheral side than the first region are provided in a junction termination portion, a first concentration gradient is provided in the first region, and a second concentration gradient larger than the first concentration gradient is provided in the second region.

Abstract: A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm?3 or higher and 6×1017 cm?3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm?3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm?3 or higher and 8×107 cm?3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm?3 or lower in a case of a junction barrier Schottky diode.

Abstract: A water-containing solid fuel drying apparatus that can efficiently dry with low energy consumption by effectively utilizing sensible heat and latent heat of a heating medium for drying, etc. is provided.

Abstract: A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm?3 or higher and 6×1017 cm?3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm?3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm?3 or higher and 8×1017 cm?3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm?3 or lower in a case of a junction barrier Schottky diode.

Abstract: In a semiconductor device having a silicon carbide device, a technique capable of suppressing variation in a breakdown voltage and achieving reduction in an area of a termination structure is provided. In order to solve the above-described problem, in the present invention, in a semiconductor device having a silicon carbide device, a p-type first region and a p-type second region provided to be closer to an outer peripheral side than the first region are provided in a junction termination portion, a first concentration gradient is provided in the first region, and a second concentration gradient larger than the first concentration gradient is provided in the second region.

Abstract: A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm?3 or higher and 6×1017 cm?3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm?3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm?3 or higher and 8×1017 cm?3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm?3 or lower in a case of a junction barrier Schottky diode.

Abstract: A developer replenishment container accommodating assembly, in which a developer replenishment container is removably put in a main body of an accommodating apparatus, replenishes a developer while rotating the developer replenishment container and includes a holding portion provided on the main body and configured to hold the developer replenishment container put in the main body of the accommodating apparatus in a replenishment position for replenishing the developer, and an engaging portion configured to engage with the developer replenishment container when it is positioned in the main assembly. In addition, a biasing member is configured to bias the engaging portion in a predetermined direction so that the developer replenishment container rotating while held by the holding portion is pressed against the holding portion by the biased engaging portion.

Abstract: A nitride semiconductor element having a high reverse breakdown voltage and a method of manufacturing the same are provided. A diode (a vertical-type SBD) has an n?-type nitride semiconductor layer (a drift region) formed on an n-type nitride semiconductor substrate, a p-type nitride semiconductor layer formed on the n?-type nitride semiconductor layer, and besides, an anode electrode formed on the p-type nitride semiconductor layer. The p-type nitride semiconductor layer has a relatively-thin first portion and a relatively-thick second portion provided so as to surround the first portion as being in contact with an outer circumference of the first portion. Also, the relatively-thin first portion of the p-type nitride semiconductor layer is formed thinner than the second portion so as to be depleted. The relatively-thick second portion of the p-type nitride semiconductor layer forms a guard ring part.

Abstract: Disclosed is a high performance nitride semiconductor having a reverse leak current characteristic with two-dimensional electron gas as a conductive layer. A desired impurity is diffused into or a nitride semiconductor to which a desired impurity is added is re-grown on the bottom surface and the side face portion of a recessed portion formed by dry etching using chlorine gas on the upper surface of a nitride semiconductor stacked film to increase resistance of the side face portion of the nitride semiconductor stacked film contacting an anode electrode, reducing the reverse leak current.

Abstract: A nitride semiconductor element having a high reverse breakdown voltage and a method of manufacturing the same are provided. A diode (a vertical-type SBD) has an n?-type nitride semiconductor layer (a drift region) formed on an n-type nitride semiconductor substrate, a p-type nitride semiconductor layer formed on the n?-type nitride semiconductor layer, and besides, an anode electrode formed on the p-type nitride semiconductor layer. The p-type nitride semiconductor layer has a relatively-thin first portion and a relatively-thick second portion provided so as to surround the first portion as being in contact with an outer circumference of the first portion. Also, the relatively-thin first portion of the p-type nitride semiconductor layer is formed thinner than the second portion so as to be depleted. The relatively-thick second portion of the p-type nitride semiconductor layer forms a guard ring part.

Abstract: A semiconductor device includes a nitride semiconductor stack having at least two hetero junction bodies where a first nitride semiconductor layer and a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer are disposed, and includes a drain electrode and, a source electrode disposed to the nitride semiconductor stack, and gate electrodes at a position put between the drain electrode and the source electrode and disposed so as to oppose them respectively in which the drain electrode and the source electrode are disposed over the surface or on the lateral side of the nitride semiconductor stack, and the gate electrode has a first gate electrode disposed in the direction of the depth of the nitride semiconductor stack and a second gate electrode disposed in the direction of the depth of the nitride semiconductor at a depth different from the first gate electrode.