Patents by Inventor Kazuhiro Motonaga

Kazuhiro Motonaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090079074
    Abstract: A semiconductor device includes a substrate having a first surface and a second surface opposing to the first surface, a semiconductor chip mounted on the first surface of the substrate, a first pad formed on the first surface of the substrate to electrically connect to a first terminal of the semiconductor chip, a second pad formed on the second surface of the substrate to electrically connect to a second terminal of the semiconductor chip, and a decoupling capacitor formed on the first surface and including the first and second pads serving as electrodes of the decoupling capacitor.
    Type: Application
    Filed: September 9, 2008
    Publication date: March 26, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Kazuhiro Motonaga
  • Patent number: 7321166
    Abstract: It is to provide a wiring board for a semiconductor integrated circuit package, which exhibits an excellent signal property and a high effect for decreasing the switching noise at the time of mounting an LSI of an area-array structure. In a multilayer wiring board for a package, which comprises, on a wiring layer of an LSI chip mount surface, a ground pad, a power supply pad, and a signal pad for mounting LSI chip, and a ground plane that extends around a group of those pads, the ground pad disposed on the inner side, among the above-described pads, is connected to the ground plane that surrounds the pad group through a connecting wiring.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: January 22, 2008
    Assignees: NEC Corporation, NEC Electronics Corporation
    Inventors: Jun Sakai, Hirobumi Inoue, Kazuhiro Motonaga
  • Publication number: 20060103004
    Abstract: It is to provide a wiring board for a semiconductor integrated circuit package, which exhibits an excellent signal property and a high effect for decreasing the switching noise at the time of mounting an LSI of an area-array structure. In a multilayer wiring board for a package, which comprises, on a wiring layer of an LSI chip mount surface, a ground pad, a power supply pad, and a signal pad for mounting LSI chip, and a ground plane that extends around a group of those pads, the ground pad disposed on the inner side, among the above-described pads, is connected to the ground plane that surrounds the pad group through a connecting wiring.
    Type: Application
    Filed: November 16, 2005
    Publication date: May 18, 2006
    Inventors: Jun Sakai, Hirobumi Inoue, Kazuhiro Motonaga