Patents by Inventor Kazuhiro NAGAMINE

Kazuhiro NAGAMINE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079517
    Abstract: A light emitting element includes: a semiconductor structure including: a substrate, an n-side nitride semiconductor layer located on the substrate, and a p-side nitride semiconductor layer located on the n-side nitride semiconductor layer, wherein a p-side nitride semiconductor side of the semiconductor structure is a light extraction face side, and an n-side nitride semiconductor side of the semiconductor structure is a mounting face side; a first protective layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the peripheral portion of the p-side nitride semiconductor layer; and a current diffusion layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the area inside of the peripheral portion. The current diffusion layer does not overlap the first protective layer in a top view.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 7, 2024
    Applicant: NICHIA CORPORATION
    Inventors: Shun KITAHAMA, Yoshiki INOUE, Kazuhiro NAGAMINE, Junya NARITA
  • Patent number: 11855238
    Abstract: A light emitting element includes: a semiconductor structure including: a substrate, an n-side nitride semiconductor layer located on the substrate, and a p-side nitride semiconductor layer located on the n-side nitride semiconductor layer, wherein a p-side nitride semiconductor side of the semiconductor structure is a light extraction face side, and an n-side nitride semiconductor side of the semiconductor structure is a mounting face side; a first protective layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the peripheral portion of the p-side nitride semiconductor layer; and a current diffusion layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the area inside of the peripheral portion. The current diffusion layer does not overlap the first protective layer in a top view.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: December 26, 2023
    Assignee: NICHIA CORPORATION
    Inventors: Shun Kitahama, Yoshiki Inoue, Kazuhiro Nagamine, Junya Narita
  • Publication number: 20210296526
    Abstract: A light emitting element includes: a semiconductor structure including: a substrate, an n-side nitride semiconductor layer located on the substrate, and a p-side nitride semiconductor layer located on the n-side nitride semiconductor layer, wherein a p-side nitride semiconductor side of the semiconductor structure is a light extraction face side, and an n-side nitride semiconductor side of the semiconductor structure is a mounting face side; a first protective layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the peripheral portion of the p-side nitride semiconductor layer; and a current diffusion layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the area inside of the peripheral portion. The current diffusion layer does not overlap the first protective layer in a top view.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 23, 2021
    Applicant: NICHIA CORPORATION
    Inventors: Shun KITAHAMA, Yoshiki INOUE, Kazuhiro NAGAMINE, Junya NARITA
  • Patent number: 11056612
    Abstract: A light emitting element includes: a semiconductor structure including: a substrate, an n-side nitride semiconductor layer containing an n-type impurity and located on the substrate, and a p-side nitride semiconductor layer containing a p-type impurity and located on the n-side nitride semiconductor layer, wherein a resistance of a peripheral portion of the p-side nitride semiconductor layer is higher than a resistance of an area inside of the peripheral portion in a top view, wherein a p-side nitride semiconductor side of the semiconductor structure is a light extraction face side, and an n-side nitride semiconductor side of the semiconductor structure is a mounting face side; and first protective layer located on an upper face of the p-side nitride semiconductor layer in a region corresponding to the peripheral portion of the p-side nitride semiconductor layer.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: July 6, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Shun Kitahama, Yoshiki Inoue, Kazuhiro Nagamine, Junya Narita
  • Publication number: 20200075797
    Abstract: A light emitting element includes: a semiconductor structure including: a substrate, an n-side nitride semiconductor layer containing an n-type impurity and located on the substrate, and a p-side nitride semiconductor layer containing a p-type impurity and located on the n-side nitride semiconductor layer, wherein a resistance of a peripheral portion of the p-side nitride semiconductor layer is higher than a resistance of an area inside of the peripheral portion in a top view, wherein a p-side nitride semiconductor side of the semiconductor structure is a light extraction face side, and an n-side nitride semiconductor side of the semiconductor structure is a mounting face side; and first protective layer located on an upper face of the p-side nitride semiconductor layer in a region corresponding to the peripheral portion of the p-side nitride semiconductor layer.
    Type: Application
    Filed: November 7, 2019
    Publication date: March 5, 2020
    Applicant: NICHIA CORPORATION
    Inventors: Shun KITAHAMA, Yoshiki INOUE, Kazuhiro NAGAMINE, Junya NARITA
  • Patent number: 10505072
    Abstract: A method for manufacturing a plurality of light emitting elements includes: providing a semiconductor wafer comprising: a substrate, an n-side nitride semiconductor layer containing an n-type impurity and located on the substrate, and a p-side nitride semiconductor layer containing a p-type impurity and located on the n-side nitride semiconductor layer; forming a protective layer on an upper face of the p-side nitride semiconductor layer in regions that include borders of areas to become the plurality of light emitting elements; reducing a resistance of the p-side nitride semiconductor in areas where no protective layer has been formed by annealing the semiconductor wafer; irradiating a laser beam on the substrate so as to form modified regions in the substrate; and obtaining a plurality of light emitting elements by dividing the semiconductor wafer in which the modified regions have been formed in the substrate.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: December 10, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Shun Kitahama, Yoshiki Inoue, Kazuhiro Nagamine, Junya Narita
  • Patent number: 10490694
    Abstract: A method of manufacturing a plurality of light emitting elements, the method includes: providing a semiconductor wafer; dividing the p-side nitride semiconductor layer into a plurality of demarcated element regions; forming a protective layer on regions including an outer periphery of an upper surface of the p-side nitride semiconductor layer of each of the plurality of demarcated element regions and exposed side surfaces in the semiconductor structure that are formed by the selectively removing the portion of the p-side nitride semiconductor layer; reducing a resistance of regions of the p-side nitride semiconductor layer; and dividing the semiconductor wafer into a plurality of light emitting elements.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: November 26, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Kazuhiro Nagamine, Yoshiki Inoue, Susumu Toko, Junya Narita
  • Publication number: 20180287009
    Abstract: A method of manufacturing a plurality of light emitting elements, the method includes: providing a semiconductor wafer; dividing the p-side nitride semiconductor layer into a plurality of demarcated element regions; forming a protective layer on regions including an outer periphery of an upper surface of the p-side nitride semiconductor layer of each of the plurality of demarcated element regions and exposed side surfaces in the semiconductor structure that are formed by the selectively removing the portion of the p-side nitride semiconductor layer; reducing a resistance of regions of the p-side nitride semiconductor layer; and dividing the semiconductor wafer into a plurality of light emitting elements.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 4, 2018
    Applicant: NICHIA CORPORATION
    Inventors: Kazuhiro NAGAMINE, Yoshiki INOUE, Susumu TOKO, Junya NARITA
  • Publication number: 20180175238
    Abstract: A method for manufacturing a plurality of light emitting elements includes: providing a semiconductor wafer comprising: a substrate, an n-side nitride semiconductor layer containing an n-type impurity and located on the substrate, and a p-side nitride semiconductor layer containing a p-type impurity and located on the n-side nitride semiconductor layer; forming a protective layer on an upper face of the p-side nitride semiconductor layer in regions that include borders of areas to become the plurality of light emitting elements; reducing a resistance of the p-side nitride semiconductor in areas where no protective layer has been formed by annealing the semiconductor wafer; irradiating a laser beam on the substrate so as to form modified regions in the substrate; and obtaining a plurality of light emitting elements by dividing the semiconductor wafer in which the modified regions have been formed in the substrate.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 21, 2018
    Applicant: NICHIA CORPORATION
    Inventors: Shun KITAHAMA, Yoshiki INOUE, Kazuhiro NAGAMINE, Junya NARITA