Patents by Inventor Kazuhiro Nakada

Kazuhiro Nakada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11912032
    Abstract: A liquid ejecting apparatus includes: a liquid ejecting head configured to eject a liquid; a liquid flowing portion coupled to the liquid ejecting head and configured to flow the liquid; and a frame that houses the liquid ejecting head and the liquid flowing portion. The frame is provided with a passage hole configured to pass the liquid flowing portion along a depth direction. when viewed in the depth direction, a portion of the liquid flowing portion disposed outside the passage hole is configured to be deformed.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: February 27, 2024
    Assignee: Seiko Epson Corporation
    Inventors: Akihiro Toya, Kazuhiro Kobayashi, Yuki Araki, Shogo Nakada, Taiki Kono
  • Publication number: 20180270538
    Abstract: The present invention provides information which serves as a useful reference when selecting content in which a user himself/herself is interested in many pieces of content. An information processing device includes an information acquisition unit which acquires information that a third person who is related to a user contributes to a website, a content search unit which searches for content relating to the information which is acquired by the information acquisition unit, and a display control unit which makes a display unit display information on a plurality of pieces of content which is viewable for the user. The display control unit makes the display unit display the information on the content which is searched for by the content search unit in the information on the plurality of pieces of content in a state of being related to information corresponding to the third person.
    Type: Application
    Filed: February 7, 2018
    Publication date: September 20, 2018
    Applicant: NEC PERSONAL COMPUTERS, LTD.
    Inventor: KAZUHIRO NAKADA
  • Patent number: 6726539
    Abstract: A ferrule end-surface polishing apparatus for polishing an end-surface of a ferrule for an optical fiber is provided. The apparatus includes a ferrule holder having a holder block capable of sandwiching a cylindrical portion of a ferrule, and a guide block for guiding the ferrule to the holder block; a polisher having a rotatable polishing board for polishing an axial end-surface of the ferrule held by the ferrule holder; and a ferrule transfer device for transferring and loading the ferrule into the ferrule holder, and for removing the ferrule therefrom after polishing. With this configuration, the ferrule polishing operation is automated.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: April 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yasushi Nishi, Kazuhiro Nakada, Makoto Kobayashi
  • Publication number: 20030200545
    Abstract: Disclosed are a program retrieval apparatus, a program video processing apparatus and a program which can retrieve a program more accurately. A control section receives an electronic program guide via a tuner or a network interface. As a sequence of characters in the electronic program guide is selected as a keyword through an operational section, the keyword is registered in a memory unit. When receiving an updated electronic program guide, the control section uses the keyword registered in the memory unit and searches programs in the electronic program guide for those programs which match with the keyword. When any program that matches with the keyword is detected, the control section displays a list of all the matched programs on an output section.
    Type: Application
    Filed: April 21, 2003
    Publication date: October 23, 2003
    Applicant: NEC Corporation
    Inventor: Kazuhiro Nakada
  • Publication number: 20020031986
    Abstract: A ferrule end-surface polishing apparatus for polishing an end-surface of a ferrule for an optical fiber, comprises ferrule holding means having a holder block capable of sandwiching a cylindrical portion of a ferrule, and a guide block for guiding the ferrule to the holder block, polishing means having a rotatable polishing board for polishing an axial end-surface of the ferrule held by the ferrule holding means, and ferrule transfer means for transferring and loading the ferrule into the ferrule holding means, and for removing the ferrule therefrom after polishing. With this configuration, the ferrule polishing operation is automated.
    Type: Application
    Filed: April 27, 2001
    Publication date: March 14, 2002
    Inventors: Yasushi Nishi, Kazuhiro Nakada, Makoto Kobayashi
  • Publication number: 20020024169
    Abstract: An apparatus and a method for manufacturing a magnet roller makes it possible to remarkably reduce defects on the surface or the inside of a magnet roller and also to control “warp” of the magnet roller sufficiently so that it does not adversely affect the functions of the magnet roller. A metal mold for magnetic field injection molding is composed of two fixed mold counterparts and a movable mold counterpart. The movable mold counterpart is moved to increase the volume of the cavity of the metal mold as a resin-bonded magnet material is injected into the mold.
    Type: Application
    Filed: August 27, 2001
    Publication date: February 28, 2002
    Applicant: Bridgestone Corporation
    Inventors: Toshimichi Nishizawa, Takatoshi Nanba, Kazuhiro Nakada
  • Patent number: 6302669
    Abstract: An apparatus for manufacturing a magnet roller makes it possible to remarkably reduce defects on the surface or the inside of a magnet roller and also to control “warp” of the magnet roller sufficiently so that it does not adversely affect the functions of the magnet roller. A metal mold for magnetic field injection molding is composed of two fixed mold counterparts and a movable mold counterpart. The movable mold counterpart is moved to increase the volume of the cavity of the metal mold as a resin-bonded magnet material is injected into the mold.
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: October 16, 2001
    Assignee: Bridgestone Corporation
    Inventors: Toshimichi Nishizawa, Takatoshi Nanba, Kazuhiro Nakada
  • Patent number: 5148396
    Abstract: Write data lines and write amplifier enable signal lines are connected to write amplifiers of a semiconductor memory device which can be switched between one-bit input and output mode configuration and multi-bit input and output mode configuration by the shared use of a single chip. Write mask data for memory write mask is supplied to the write amplifiers by the write amplifier enable signal lines.
    Type: Grant
    Filed: February 27, 1990
    Date of Patent: September 15, 1992
    Assignee: NEC Corporation
    Inventor: Kazuhiro Nakada
  • Patent number: 5124947
    Abstract: A semiconductor memory device comprises memory cells arranged in matrix, a plurality of bit line pairs respectively coupled to the columns of the memory cells, a plurality of word lines respectively coupled to the rows of the memory cells and selectively activating the memory cells for porducing small differences in voltage level on the plurality of bit line pairs, respectively, a plurality of sense amplifier circuits respectively coupled to the plurality of bit line pairs and selectively coupling component bit lines of the bit lines pairs to first and second voltage sources depending upon the small differences, first and second data signal lines, a column selector circuit coupling the first and second data signal lines with one of the plurality of bit line pairs, and a pull-up circuit coupled between the first voltage source and the first and second data signal lines for allowing voltage levels on the first and second data signal lines to vary within a predetermined voltage range, wherein a small current pat
    Type: Grant
    Filed: November 19, 1990
    Date of Patent: June 23, 1992
    Assignee: NEC Corporation
    Inventor: Kazuhiro Nakada
  • Patent number: 5079747
    Abstract: A semiconductor memory device is installed in one of a single data output and a parallel data output model, and a single data output unit associated with a first diagnostic unit and a parallel data output unit with a second diagnostic unit are incorporated in the semiconductor memory device for selective usage, wherein a first number of data bits read out from memory cells are subjected to diagnosis for supplying a plurality of first diagnostic signals in the signal data output model, however, the first diagnostic signals are further subjected to diagnosis for producing a single second diagnostic signal in the parallel data output model without supplying the first diagnostic signals to the outside thereof so that the internal wiring arrangement is simplified and occupies a small amount of real estate.
    Type: Grant
    Filed: March 29, 1991
    Date of Patent: January 7, 1992
    Assignee: NEC Corporation
    Inventor: Kazuhiro Nakada
  • Patent number: 4996446
    Abstract: An output circuit of a semiconductor circuit has a reverse bias voltage generator which comprises a ring oscillating circuit, a reverse bias voltage generating circuit and a switching circuit. The output circuit is of the type having first and second output N-(P-)channel MOS transistors connected in series, an output terminal being provided at the intermediate position of the transistors. The ring oscillating circuit is activated for oscillation only when an ouptut enabling signal is of a zero potential indicative of disabling outputting of an input data signal. The reverse bias voltage generating circuit generates a reverse bias voltage lower (higher) than the ground potential based on the oscillation output of the oscillating circuit. The switching circuit supplies a reverse bias voltage to the gate of the first output N-(P-)channel MOS transistor only when a bias instruction signal, i.e.
    Type: Grant
    Filed: September 27, 1989
    Date of Patent: February 26, 1991
    Assignee: NEC Corporation
    Inventor: Kazuhiro Nakada
  • Patent number: 4870621
    Abstract: A dual port memory which enables consecutive access operations from an arbitrary column address and is fabricated on a reduced area of a semiconductor chip. The memory includes a memory array, a random access peripheral circuit for effecting random access to the array and having a column decoder, and a serial access peripheral circuit having a shift register for serially selecting the columns of the array and a control circuit for determining the state of the shift register in accordance with the output of the column register.
    Type: Grant
    Filed: November 27, 1987
    Date of Patent: September 26, 1989
    Assignee: NEC Corporation
    Inventor: Kazuhiro Nakada