Patents by Inventor Kazuhiro Segawa
Kazuhiro Segawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12264095Abstract: One aspect is a reflective member, which has a laminated structure in which transparent quartz glass members are formed on an upper surface and a lower surface of an opaque siliceous sintered powder layer. The opaque siliceous sintered powder layer has a thickness of 0.1 mm or more and a thickness distribution of ±0.05 mm or less. When a load is applied to each of the transparent quartz glass members on an upper surface and a lower surface of the laminated structure in a direction parallel to the laminated structure, the reflective member is fractured at a load of 5 N or more per square centimeter. The laminated structure includes a semi-transparent portion having a width of 0.01 mm or less, which has an intermediate opacity between an opacity of the opaque siliceous sintered powder layer and an opacity of each of the transparent quartz glass members.Type: GrantFiled: August 17, 2020Date of Patent: April 1, 2025Assignees: Shin-Etsu Quartz Products Co., Ltd., Heraeus Quarzglas GmbH & Co. KGInventors: Toru Segawa, Kazuhiro Yamaguchi, Tomonori Watanabe, Daiki Fujita
-
Publication number: 20240045408Abstract: A dynamic sampling method and device for semiconductor manufacture are provided. The dynamic sampling method includes: generating an N-dimensional virtual image of a wafer based on a design rule and at least one of a quality control data and context data; measuring a critical pattern in the N-dimensional virtual image to generate a virtual metrology result by using a virtual metrology; determining whether the virtual metrology result is larger than a threshold; not performing a measurement on the wafer in a case that the virtual metrology result is larger than the threshold; and performing the measurement on the wafer in a case that the virtual metrology result is not larger than the threshold.Type: ApplicationFiled: August 2, 2022Publication date: February 8, 2024Applicant: Winbond Electronics Corp.Inventors: Kazuhiro Segawa, Chiang-Sheng Liu
-
Publication number: 20230375914Abstract: A semiconductor manufacturing apparatus and a semiconductor manufacturing method thereof are provided. Wafers are grouped into a first wafer group and a second wafer group according to alignment mark position errors of the wafers and a first threshold value. The alignment mark position errors of the first wafer group are greater than the first threshold value, and the alignment mark position errors of the second wafer group are less than or equal to the first threshold value. A feedforward position correction value is calculated according to a difference between the alignment mark position errors of the first wafer group and a reference error value. A lithography process is performed on the wafers according to the feedforward position correction value.Type: ApplicationFiled: May 23, 2022Publication date: November 23, 2023Applicant: Winbond Electronics Corp.Inventors: Kazuhiro Segawa, Isao Tanaka
-
Patent number: 11016391Abstract: According to one embodiment, a first test process concerning a light-exposure process is performed by forming a first lower layer and a first upper layer on a first substrate. A second test process concerning a light-exposure process is performed by forming a second lower layer and a second upper layer on a second substrate. A correction model is created on a basis of results obtained in the first test process and the second test process. A manufacturing process is performed by forming a third lower layer and a third upper layer on a third substrate. In the manufacturing process, an overlay estimation correction value is calculated by using the correction model, based on a first pattern position deviation amount, a step processing history in the manufacturing process, a second pattern position deviation amount, and an overlay residual, and the overlay estimation correction value is used in a light-exposure process.Type: GrantFiled: February 28, 2019Date of Patent: May 25, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventor: Kazuhiro Segawa
-
Publication number: 20200073256Abstract: According to one embodiment, a first test process concerning a light-exposure process is performed by forming a first lower layer and a first upper layer on a first substrate. A second test process concerning a light-exposure process is performed by forming a second lower layer and a second upper layer on a second substrate. A correction model is created on a basis of results obtained in the first test process and the second test process. A manufacturing process is performed by forming a third lower layer and a third upper layer on a third substrate. In the manufacturing process, an overlay estimation correction value is calculated by using the correction model, based on a first pattern position deviation amount, a step processing history in the manufacturing process, a second pattern position deviation amount, and an overlay residual, and the overlay estimation correction value is used in a light-exposure process.Type: ApplicationFiled: February 28, 2019Publication date: March 5, 2020Applicant: Toshiba Memory CorporationInventor: Kazuhiro Segawa
-
Patent number: 10269661Abstract: According to an embodiment, a manufacturing system for a semiconductor device includes a first processing device and a second processing device, a measurement section, and an analysis section. The first processing device and the second processing device are adapted to perform a film formation process on a substrate in a wafer. The measurement section is adapted to measure a first value related to a shape of the wafer after film formation by the first processing device, and then measure a second value related to a distortion of the wafer based on the first value. The analysis section is adapted to change a film formation condition of the second processing device based on processing information of the first processing device, the second value, and information of the second processing device.Type: GrantFiled: September 6, 2017Date of Patent: April 23, 2019Assignee: Toshiba Memory CorporationInventor: Kazuhiro Segawa
-
Publication number: 20180277451Abstract: According to an embodiment, a manufacturing system for a semiconductor device includes a first processing device and a second processing device, a measurement section, and an analysis section. The first processing device and the second processing device are adapted to perform a film formation process on a substrate in a wafer. The measurement section is adapted to measure a first value related to a shape of the wafer after film formation by the first processing device, and then measure a second value related to a distortion of the wafer based on the first value. The analysis section is adapted to change a film formation condition of the second processing device based on processing information of the first processing device, the second value, and information of the second processing device.Type: ApplicationFiled: September 6, 2017Publication date: September 27, 2018Applicant: Toshiba Memory CorporationInventor: Kazuhiro SEGAWA
-
Patent number: 10054856Abstract: According to one embodiment, there is provided an exposure method. The method includes attaching a thin film sheet thermally shrinkable onto a rear face of a wafer. The method includes heating the wafer provided with the thin film sheet attached thereon, and deforming the wafer into a shape projecting on a front face side of the wafer. The method includes fixing the deformed wafer onto a stage by vacuum suction holding from a rear face side of the wafer. The method includes performing exposure to the fixed wafer.Type: GrantFiled: April 22, 2015Date of Patent: August 21, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kentaro Matsunaga, Kazuhiro Segawa
-
Patent number: 9952505Abstract: According to one embodiment, an imprint device includes a holding unit, a mounting unit, a moving unit, a curing unit, a pressing portion, and a detecting portion. The holding unit holds template having a pattern portion pressed onto a transfer portion provided on a substrate. The mounting unit mounts the substrate. The moving unit is provided on at least either the holding unit or the mounting unit. The moving unit moves the holding unit and the mounting unit in directions approaching each other or directions away from each other. The curing unit cures the transfer portion onto which the pattern portion of the template is pressed. The pressing portion pushes the template pressed onto the transfer portion in a direction intersecting a pressing direction of the template. The detecting portion detects a position of the template pushed by the pressing portion.Type: GrantFiled: September 9, 2014Date of Patent: April 24, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yosuke Okamoto, Nobuhiro Komine, Kazuhiro Segawa, Manabu Takakuwa, Kentaro Kasa
-
Patent number: 9941177Abstract: A pattern accuracy detecting apparatus includes a stage for supporting a substrate, an optical warpage detecting unit that measures a shape of a substrate disposed on the stage, an optical pattern detection unit that detects a position of a pattern on the substrate, and a processing unit that corrects the detected pattern position based on the measured shape of the substrate.Type: GrantFiled: August 31, 2016Date of Patent: April 10, 2018Assignee: Toshiba Memory CorporationInventors: Kentaro Kasa, Kazuya Fukuhara, Kazutaka Ishigo, Manabu Takakuwa, Yoshinori Hagio, Kazuhiro Segawa, Yuki Murasaka, Tetsuya Kugimiya, Yuu Yamayose, Yosuke Okamoto
-
Patent number: 9929103Abstract: According to one embodiment, an optical element branches reflection light from a first mark and a second mark having different focus positions, a first imaging element captures an image of the first mark based on a first branch light branched by the optical element, a second imaging element captures an image of the second mark based on a second branch light branched by the optical element, and an arithmetic processing unit that calculates a misalignment between the first mark and the second mark based on a result of superimposition of the image of the first mark and the image of the second mark.Type: GrantFiled: June 19, 2015Date of Patent: March 27, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Kazuhiro Segawa
-
Publication number: 20170271214Abstract: A pattern accuracy detecting apparatus includes a stage for supporting a substrate, an optical warpage detecting unit that measures a shape of a substrate disposed on the stage, an optical pattern detection unit that detects a position of a pattern on the substrate, and a processing unit that corrects the detected pattern position based on the measured shape of the substrate.Type: ApplicationFiled: August 31, 2016Publication date: September 21, 2017Inventors: Kentaro KASA, Kazuya FUKUHARA, Kazutaka ISHIGO, Manabu TAKAKUWA, Yoshinori HAGIO, Kazuhiro SEGAWA, Yuki MURASAKA, Tetsuya KUGIMIYA, Yuu YAMAYOSE, Yosuke OKAMOTO
-
Patent number: 9625831Abstract: According to one embodiment, a controller calculates wafer alignment residuals from results of wafer alignment measurement and calculates shape change displacement residuals from the surface shape of a wafer. Further, the controller calculates first conversion coefficients that are ratios of the wafer alignment residuals to the shape change displacement residuals and generates fine wafer alignment residual data by using the first conversion coefficients. Furthermore, the controller generates correction information in which first correction values at the time of the exposure processing are calculated for every shot on the wafer by using the fine wafer alignment residual data. Then, the controller controls exposure processing in an exposure unit by using the correction information corresponding to the shot of the wafer.Type: GrantFiled: February 9, 2016Date of Patent: April 18, 2017Assignee: Kabushiki Kaisha ToshibaInventor: Kazuhiro Segawa
-
Publication number: 20160240423Abstract: According to one embodiment, there is provided an exposure method. The method includes attaching a thin film sheet thermally shrinkable onto a rear face of a wafer. The method includes heating the wafer provided with the thin film sheet attached thereon, and deforming the wafer into a shape projecting on a front face side of the wafer. The method includes fixing the deformed wafer onto a stage by vacuum suction holding from a rear face side of the wafer. The method includes performing exposure to the fixed wafer.Type: ApplicationFiled: April 22, 2015Publication date: August 18, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Kentaro MATSUNAGA, Kazuhiro SEGAWA
-
Publication number: 20160223321Abstract: According to one embodiment, an optical element branches reflection light from a first mark and a second mark having different focus positions, a first imaging element captures an image of the first mark based on a first branch light branched by the optical element, a second imaging element captures an image of the second mark based on a second branch light branched by the optical element, and an arithmetic processing unit that calculates a misalignment between the first mark and the second mark based on a result of superimposition of the image of the first mark and the image of the second mark.Type: ApplicationFiled: June 19, 2015Publication date: August 4, 2016Applicant: Kabushiki Kaisha ToshibaInventor: Kazuhiro SEGAWA
-
Patent number: 9396299Abstract: Reticle marks are arranged at a plurality of places in a kerf region of a reticle, the area of a polygon with apexes at arrangement positions of the reticle marks is calculated, and the arrangement positions of the reticle marks are decided based on results of calculation of the area of the polygon.Type: GrantFiled: September 4, 2014Date of Patent: July 19, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Shinichi Nakagawa, Nobuhiro Komine, Kazuhiro Segawa, Manabu Takakuwa, Motohiro Okada
-
Publication number: 20160020099Abstract: According to one embodiment, first, an embedment material is embedded between linear core material patterns in such a manner that a height thereof becomes lower than a height of each of the core material patterns. Then, a shrink agent is supplied and solidified on the embedment material. Subsequently, the solidified shrink agent and the embedment material are removed and a spacer film is formed on an object of processing. Then, the spacer film is etched-back and a spacer pattern is formed by removal of the core material patterns. The solidified shrink agent which is formed in such a manner that a width of the spacer pattern becomes narrow in a region corresponding to a position where the shrink agent, in a sectional surface vertical to an extended direction of the spacer pattern is supplied is removed.Type: ApplicationFiled: December 17, 2014Publication date: January 21, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Kazuhiro SEGAWA, Nobuhiro KOMINE, Kentaro MATSUNAGA, Takehiro KONDOH, Shinichi NAKAGAWA
-
Patent number: 9239526Abstract: According to one embodiment, an exposure apparatus includes a light blocking unit that blocks an exposure light reflected on a reflective mask at a part other than an aperture; a detection unit that measures a light intensity of the exposure light passed through the light blocking unit; and a calculation unit that calculates, based on the light intensity, a transfer characteristic when a pattern on the reflective mask is transferred to a substrate. In the light blocking unit, a position on an aperture plane and a position in an optical axis direction of the exposure light are adjusted. The calculation unit calculates the transfer characteristic based on the position in the optical axis direction in which the light intensity is maximized.Type: GrantFiled: September 11, 2013Date of Patent: January 19, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hidenori Sato, Kazuhiro Segawa, Nobuhiro Komine
-
Publication number: 20150371946Abstract: In the present invention, in a twin plug-forming step, a conductive material is removed so as to form a groove for separating a diffusion layer (29), a diffusion layer-separating insulating film (30) is implanted so as to separate a diffusion layer, and contact plugs (25b) and (25c) are separated. In the twin plug-forming step, a second conductive material is implanted in a contact hole surrounded by a bit line (16) between word lines (10b) and (10d), and is separated in a second direction. The conductive material was implanted in a dummy word line in the related art.Type: ApplicationFiled: February 6, 2014Publication date: December 24, 2015Inventor: Kazuhiro Segawa
-
Publication number: 20150339423Abstract: Reticle marks are arranged at a plurality of places in a kerf region of a reticle, the area of a polygon with apexes at arrangement positions of the reticle marks is calculated, and the arrangement positions of the reticle marks are decided based on results of calculation of the area of the polygon.Type: ApplicationFiled: September 4, 2014Publication date: November 26, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Shinichi Nakagawa, Nobuhiro Komine, Kazuhiro Segawa, Manabu Takakuwa, Motohiro Okada