Patents by Inventor Kazuhiro Shimotori
Kazuhiro Shimotori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6423335Abstract: A composition comprising modified milk powder, and glutamine and/or a peptide containing glutamine.Type: GrantFiled: November 3, 2000Date of Patent: July 23, 2002Assignee: Ajinomoto Co., Inc.Inventors: Kazunori Mawatari, Susumu Shibahara, Takeo Ueda, Makoto Takeuchi, Kazuhiro Shimotori
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Patent number: 4694432Abstract: A semiconductor memory device comprises a plurality of row decoder circuits connected with word lines for selecting memory cells. The row decoder circuits include normal row decoder circuits and spare row decoder circuits which can be selected in place of a normal row decoder circuit in case where a fault occurs in a memory cell selected by a word line connected to the normal row decoder circuit. An RAS signal (precharge signal) is applied to an output line (12) of a normal row decoder circuit through a precharge bus (31). A link element (11p) is inserted in the precharge bus (31). The link element (11p) is an element which can be melted by a laser beam, whereby the normal row decoder circuit associated is maintained in a non-selective state. A clamp circuit (14) is also connected to the output line (12).Type: GrantFiled: March 6, 1985Date of Patent: September 15, 1987Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideshi Miyatake, Kazuyasu Fujishima, Kazuhiro Shimotori
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Patent number: 4658379Abstract: A semiconductor memory device with a laser programmable redundancy circuit, which includes: a plurality of decoders for selecting a row or column of the memory; at least one spare decoder which is selected instead of a decoder connected to a faulty memory cell; a link element inserted in series with the precharging transistor and connected between the power supply and the decoder output line; a signal generator which generates a non-selection signal for making the object decoder unselected only when a spare decoder is selected, the signal generator being provided in the spare decoder; and a transistor, having a gate to which the non-selection signal is input, with the drain and the source thereof being connected to the decoder output and ground, respectively, the transistor being provided in the decoder.Type: GrantFiled: October 30, 1984Date of Patent: April 14, 1987Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuyasu Fujishima, Kazuhiro Shimotori, Hideyuki Ozaki, Hideshi Miyatake, Masahiro Tomisato
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Patent number: 4641286Abstract: A semiconductor memory device in which at least a line decoder or a column decoder in multiplex form is provided to select one line selection signal or column selection signal. When the line decoder or column decoder is defective, or when the word line or bit line associated with the line decoder or column decoder involves a defective bit, the defective line decoder, column decoder, word line or bit line is inactivated. The inactivated line decoder or column decoder is replaced with an auxiliary line decoder or column decoder.Type: GrantFiled: February 16, 1984Date of Patent: February 3, 1987Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuhiro Shimotori, Kazuyasu Fujishima, Hideyuki Ozaki, Hideshi Miyatake
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Patent number: 4593382Abstract: An MOS dynamic memory device is improved in operation by adding a cell plate voltage control circuit to terminals of the word lines and connected to respective cell plates. In operation, the cell plate is recharged after discharged during with a time which a word line remains driven.Type: GrantFiled: September 16, 1982Date of Patent: June 3, 1986Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuyasu Fujishima, Kazuhiro Shimotori, Hideyuki Ozaki, Takao Nakano
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Patent number: 4586167Abstract: Disclosed is a semiconductor memory device which is operable in a selected one of page mode and nibble mode, depending upon the length of time in which an external column address strobe signal stays at a specific level. The semiconductor memory device comprises a circuit for discriminating the length of time where the external column address strobe signal is at a specific level with a predetermined period of time. Data is outputted in page mode in response to one of results of such discrimination and in nibble mode in response to the other result of the discrimination. The discriminating circuit may comprise a second internal column address strobe signal generator and a delay circuit. The second internal column address strobe signal generator includes a NAND circuit at its first stage, and the delay circuit is designed to have different delay times at the building-up and downward edges of an input signal applied thereto.Type: GrantFiled: January 4, 1984Date of Patent: April 29, 1986Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuyasu Fujishima, Kazuhiro Shimotori, Hideyuki Ozaki, Hideshi Miyatake
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Patent number: 4575825Abstract: Disclosed is a semiconductor memory device which is one of three types of semiconductor memory devices, one operable only in page mode, one operable only in nibble and one operable selectively in page mode or nibble mode, being obtained from a partially unconnected semiconductor memory device through alternations in a portions in wiring. The semiconductor memory device includes first and second internal column address strobe signal generator. The second internal column address strobe signal generator has at the first stage thereof a NAND circuit one of inputs to which determines the type of the semiconductor memory device depending on which of three kinds of signals is selected as the input. Selection of such an input is effected by an aluminum wiring process using a mask. Such selection of the input causes variation in the input response characteristics of the output of the second internal column address strobe signal generator, thus providing a desired response appropriate for the selected mode or modes.Type: GrantFiled: January 4, 1984Date of Patent: March 11, 1986Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideyuki Ozaki, Kazuhiro Shimotori, Hideshi Miyatake
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Patent number: 4551741Abstract: A semiconductor memory device having two layers of polycrystal silicon and having an insulated gate field effect transistor as a fundamental element including by using a first layer of polycrystalline silicon serving as an electrode of a capacitor and a bit line and a second layer of polycrystalline silicon serving as a gate electrode of the transistor.Type: GrantFiled: December 29, 1983Date of Patent: November 5, 1985Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuhiro Shimotori, Hideyuki Ozaki
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Patent number: 4455628Abstract: The disclosure described a substrate bias generating circuit in which an internal RAS (Row Address Strobe) signal and an internal CAS (Column Address Strobe) signal, both of which are synchronized with an external RAS signal and external CAS supplied from outside in addition to self-oscillator, activate circuits comprising capacitors and rectifying elements respectively so as to reduce wattage dissipation thereof during holding time of RAM and be obtained increased charge pump current during operation thereof.Type: GrantFiled: November 4, 1982Date of Patent: June 19, 1984Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideyuki Ozaki, Kazuyasu Fujishima, Kazuhiro Shimotori
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Patent number: 4384218Abstract: A substrate bias generator which includes: an MOS capacitor having an electrically insulating film located between two electrodes, one of which is disposed on one main face of a P.sup.- semiconductor substrate; and first, second and a third N.sup.+ semiconductor regions disposed in a spaced relationship on that main face. The first and second regions form a grounded source and a drain of an MOSFET having a gate connected to both the drain and the other electrode of the capacitor. The second and third regions form a source and a drain of another MOSFET having a gate connected to both the drain and the other main face of the substrate. A train of square pulses is supplied to the one electrode of the capacitor.Type: GrantFiled: July 23, 1980Date of Patent: May 17, 1983Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuhiro Shimotori, Toshio Ichiyama, Yooichi Tobita
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Patent number: 4377756Abstract: An insulated gate field-effect transistor (MOS.multidot.FET) formed as a basic element of an integrated circuit formed together with a substrate bias circuit in a semiconductor substrate having negative potential. In the substrate bias circuit, semiconductor regions (p.sup.+ -regions) having impurity concentrations higher than that of the semiconductor substrate (p-type) are formed between the semiconductor regions (n.sup.+ -region) and the semiconductor substrate (p-type) to form n.sup.+ p.sup.+ p-diodes.Type: GrantFiled: February 12, 1980Date of Patent: March 22, 1983Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tsutomu Yoshihara, Kazuhiro Shimotori, Yasuji Nagayama
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Patent number: 4255756Abstract: The disposed substrate bias generator comprises a capacitor including an electrically insulating film sandwiched between two electrodes one of which is disposed on one main face of a p.sup.- semiconductor substrate through another electrically insulating film, and a first, a second and a third N.sup.+ semiconductor region disposed in spaced relationship on the same main face. The first and second regions form a grounded source and a drain of an MOSFET connected to both its gate and one of the electrodes of the capacitor. The second and third regions form a source and a drain of another MOSFET connected to both its gate and the other main face of the substrate. A signal is applied to the other electrode of the capacitor.Type: GrantFiled: January 3, 1980Date of Patent: March 10, 1981Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuhiro Shimotori, Takao Nakano, Yasuzi Nagayama
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Patent number: RE35141Abstract: The disclosure described a substrate bias generating circuit in which an internal RAS (Row Address Strobe) signal and an internal CAS (Column Address Strobe) signal, both of which are synchronized with an external RAS signal and external CAS supplied from outside in addition to self-oscillator, activate circuits .[.comprising.]. .Iadd.including .Iaddend.capacitors and rectifying elements respectively so as to reduce wattage dissipation thereof during holding time of RAM and be obtained increased charge pump current during operation thereof.Type: GrantFiled: October 29, 1993Date of Patent: January 9, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideyuki Ozaki, Kazuyasu Fujishima, Kazuhiro Shimotori