Abstract: A manufacture method is provided for forming a semiconductor device. The method includes: forming a plurality of gate electrodes through etching a conductive film deposited on a semiconductor substrate; forming a first nitride film to cover the gate electrodes; partially exposing the semiconductor substrate in a region between adjacent two of the gate electrodes through performing an etch-back process on the first nitride film; thermally oxidizing a residual of the gate electrode film remaining in the region between the adjacent two of the gate electrodes to change the residual into an thermal oxide film; and forming a contact in the region between the adjacent two of the gate electrodes.

Abstract: A manufacture method is provided for forming a semiconductor device. The method includes: forming a plurality of gate electrodes through etching a conductive film deposited on a semiconductor substrate; forming a first nitride film to cover the gate electrodes; partially exposing the semiconductor substrate in a region between adjacent two of the gate electrodes through performing an etch-back process on the first nitride film; thermally oxidizing a residual of the gate electrode film remaining in the region between the adjacent two of the gate electrodes to change the residual into an thermal oxide film; and forming a contact in the region between the adjacent two of the gate electrodes.

Abstract: A semiconductor memory and its manufacturing method enable high-integrated memory cell to be realized easily. The semiconductor memory according to the present invention has an impurity diffusion region with a second conductive type that is opposite to a first conductive type on a surface of a semiconductor substrate with the first conductive type. Further, the semiconductor memory has structure in which there are provided a floating gate electrode formed on the semiconductor substrate via a gate insulator, and a control gate electrode formed on the floating gate electrode via an interelectrode insulating film. Furthermore, there are provided the gate insulator on the surface of the semiconductor substrate with the exception of an impurity diffusion region, and a third insulating film with film thickness thicker than that of the gate insulator on the surface of the impurity diffusion region.

Abstract: A semiconductor device having buried oxide film (11) and a diffusion layer (12) formed in an alternating pattern. A CMP method can be used to create a planar surface. Polycide (13) can be formed on buried oxide film (11). An interlayer film (14) can be formed on buried oxide film (11), diffusion layer (12), and polycide (13). Contact holes (15) can be formed in interlayer layer (12) above polycide. A plug (17) including a barrier layer (16) can be formed in contact holes. A pad electrode (18) can be formed with plugs (17) providing an electrical connection between pad electrode (18) and polycide (13). In this manner, barrier layer (16) and plugs (17) can provide an anchor for the pad electrode (18). Peeling may be prevented when stress is applied to the pad electrode (18) during the bonding process.

Abstract: A semiconductor memory device, comprising a substrate of a first conductivity type, a plurality of first diffusion regions in which atoms of a first dopant of a second conductivity type opposite to the first conductivity type are diffused, the first diffusion regions being disposed in the substrate and spaced one after another to define a channel between two adjacent first diffusion regions, a plurality of second diffusion regions in which atoms of a second dopant of the first conductivity type are diffused, the second diffusion regions being disposed in the substrate and defining two opposite boundaries of each channel with the two adjacent first diffusion regions, a plurality of gate oxide regions on the channels; and a plurality of word lines extending orthogonal to a direction in which the first diffusion regions extend and further wherein two adjacent second diffusion regions cover two side surface portions of each of the first diffusion regions with a lower surface portion of the first diffusion region

Abstract: A semiconductor memory comprises a gate electrode formed on a gate oxide film formed in each of active regions on a principal surface of a semiconductor substrate, grooves formed in self alignment with the gate electrode and to penetrate the inside of the semiconductor substrate, a buried digit line formed of a diffused layer which is formed at an inner surface of each of the grooves and which is of a conductivity type opposite to that of the semiconductor substrate, a chemical vapor deposition (CVD) oxide film formed to cover the surface of each of the grooves and at least a portion of a side surface of the gate electrode, a borophsphosilicate glass (BPSG) film filled up in the grooves, and a word line formed on the principal surface of the semiconductor substrate to extend orthogonally to the grooves, and constituting the gate electrode on the active region and functioning as an interconnection layer on the grooves.

Abstract: A semiconductor memory having MOS transistor devices whose gate length is less than half a micron, and a method of producing the same are disclosed. The memory reduces parasitic resistance outside of channels and thereby allows the ON current for the MOS transistors or memory cell transistors to be increased. In addition, the memory guarantees a source-drain withstanding voltage and the reversal threshold voltage of device separating oxide films. The memory can therefore be highly integrated and is reliable.

Abstract: A semiconductor memory comprises a gate electrode formed on a gate oxide film formed in each of active regions on a principal surface of a semiconductor substrate, grooves formed in self alignment with the gate electrode and to penetrate the inside of the semiconductor substrate, a buried digit line formed of a diffused layer which is formed at an inner surface of each of the grooves and which is of a conductivity type opposite to that of the semiconductor substrate, a CVD oxide film formed to cover the surface of each of the grooves and at least a portion of a side surface of the gate electrode, a BPSG film filled up in the grooves, and a word line formed on the principal surface of the semiconductor substrate to extend orthogonally to the grooves, and constituting the gate electrode on the active region and functioning as an interconnection layer on the grooves.

Abstract: A semiconductor memory and its manufacturing method enable high-integrated memory cell to be realized easily. The semiconductor memory according to the present invention has an impurity diffusion region with a second conductive type that is opposite to a first conductive type on a surface of a semiconductor substrate with the first conductive type. Further, the semiconductor memory has structure in which there are provided a floating gate electrode formed on the semiconductor substrate via a gate insulator, and a control gate electrode formed on the floating gate electrode via an interelectrode insulating film. Furthermore, there are provided the gate insulator on the surface of the semiconductor substrate with the exception of an impurity diffusion region, and a third insulating film with film thickness thicker than that of the gate insulator on the surface of the impurity diffusion region.

Abstract: A semiconductor device having buried oxide film (11) and a diffusion layer (12) formed in an alternating pattern. A CMP method can be used to create a planar surface. Polycide (13) can be formed on buried oxide film (11). An interlayer film (14) can be formed on buried oxide film (11), diffusion layer (12), and polycide (13). Contact holes (15) can be formed in interlayer layer (12) above polycide. A plug (17) including a barrier layer (16) can be formed in contact holes. A pad electrode (18) can be formed with plugs (17) providing an electrical connection between pad electrode (18) and polycide (13). In this manner, barrier layer (16) and plugs (17) can provide an anchor for the pad electrode (18). Peeling may be prevented when stress is applied to the pad electrode (18) during the bonding process.

Abstract: A fabrication process of a mask ROM is disclosed, which process is effective to suppress the occurrence of punch-through of a memory cell transistor. According to the process, the surface of a P conductivity-type silicon substrate is subjected to thermal oxidation to grow oxides to form a pad oxide film. A silicon nitride film, which acts as an oxidation resisting film, is deposited on the pad oxide film. A resist is formed on the silicon nitride film. The resist has openings where bit lines are to extend. Using the resist as a mask, the silicon nitride film is selectively etched away. Using the resist as a mask, ions of arsenic (As) are introduced by ion implantation to the substrate for formation of N conductivity-type diffusion regions in the subsequent thermal oxidation. These N conductivity-type diffusion regions act as the bit lines.

Abstract: A NOR type mask ROM has embedded digit lines arranged in stripes sandwiching an active region on a semiconductor substrate, a gate insulating film formed on the surface of the semiconductor substrate, and word lines formed in stripes in a direction perpendicular to the embedded digit lines on the gate insulating film. The embedded digit line is composed of a first groove provided in the surface side region of the semiconductor substrate, a second groove provided at the substrate lower side of the first groove, an insulating film provided on an inner surface of the second groove, and a semiconductor layer doped with an impurity of other conductive type embedded in the first groove and second groove. An impurity diffusion layer of other conductive type functioning as the source and drain is formed by diffusing the impurity contained in the semiconductor layer through the side of the first groove in the active region.

Abstract: A fabrication process of a mask ROM is disclosed, which process is effective to suppress the occurrence of punch-through of a memory cell transistor. According to the process, the surface of a P conductivity-type silicon substrate is subjected to thermal oxidation to grow oxides to form a pad oxide film. A silicon nitride film, which acts as an oxidation resisting film, is deposited on the pad oxide film. A resist is formed on the silicon nitride film. The resist has openings where bit lines are to extend. Using the resist as a mask, the silicon nitride film is selectively etched away. Using the resist as a mask, ions of arsenic (As) are introduced by ion implantation to the substrate for formation of N conductivity-type diffusion regions in the subsequent thermal oxidation. These N conductivity-type diffusion regions act as the bit lines. Using the resist as a mask, ions of boron (B) are introduced by ion implantation for formation of P.sup.

Abstract: In a method for forming a groove-type isolation area, an insulating pattern is formed by a selective oxidation process or a LOCOS process on a semiconductor substrate. The semiconductor substrate is etched with a mask of the insulating pattern to create a groove in the semiconductor substrate. An insulating layer is buried in the groove to form the groove-type isolation area.

Abstract: A NAND type mask ROM having a gate length of one half micron or below is disclosed. For the fabrication of this device, gate electrodes are formed on a gate insulating film which is on a P-type silicon substrate and in which a memory cell region and a peripheral transistor are separately defined by a field oxide film. Then, N.sup.- -type diffusion layers are formed, and then an insulating layer is deposited by a biased ECRCVD process. The insulating film is not formed on edges of the memory cell gate electrodes so that, when the entire surface of the insulating film is etched-back, side walls are formed only in the peripheral transistor region. By subsequently forming N.sup.+ -type diffusion layers, N-channel cell transistors and an N-channel LDD transistor 11 are formed in a self-aligned form. The resulting structure permits increasing memory cell transistor "on" current without increasing the number of steps and number of masks.

Abstract: A method of fabricating a semiconductor device incorporates the steps of forming in succession a gate insulting film, a polycrystalline silicon film and a first insulating film on a semiconductor substrate surface, and etching a portion of the first insulating film, the polycrystalline silicon film and the gate insulating film to expose the semiconductor substrate. The exposed semiconductor substrate is etched to form a trench. The trench is then buried by depositing a second insulating film and thereafter a third insulating film. The second and third insulating films are then etched with the third insulating film being etched at a higher rate than the second insulating film. The polycrystalline silicon film is used as a stopper to leave behind the second and third insulating films in the trench. A fourth insulating film is deposited, and then etched again using the polycrystalline silicon film as a stopper. The side walls of the trench are thus coated with the fourth insulating film.

Abstract: A semiconductor mask ROM device has word lines embedded in a surface portion of a silicon substrate, a gate insulating layer covering the word lines and a silicon strips extending over the gate insulating layer and providing channel regions over the word lines, and the silicon strips are physically separated without a thick field oxide layer, thereby increasing the integration density of the memory cells.

Abstract: The invention provides a method of fabricating a semiconductor device by forming, on a P-type silicon substrate, a memory cell portion partitioned with a field oxide film, forming trenches in self-alignment with a polycrystalline silicon film which act as gate electrodes in the semiconductor device, completely burying second and third oxide films in the trenches, removing the third oxide film near the end of the field oxide film by using a second resist film as a mask and thereafter etching-back the whole surface to cause the second and third oxide films to remain only in the trenches. According to the method, the oxide film can be stably buried in the trenches.

Abstract: A method of producing a highly reliable mask ROM and the product produced by the method are disclosed. The method is characterized by comprising the steps of forming low doped source-drains to relax the electric field between the gate electrode and drain, thereby suppressing the creation of hot carriers, and of depositing dielectrics of a predetermined thickness between neighboring gates to control the projection range of impurities implanted into the source-drain region of the bit into which data is to be written, the thickness of the dielectrics being determined such that the projection range does not exceed the junction depth of the source-drain in order to preclude the formation of parasitically doped layers which cause punch-through across an unwritten transistor.

Abstract: A semiconductor device is provided with an isolation region for isolating the semiconductor device from an adjacent semiconductor device provided commonly on a semiconductor substrate. The isolation region includes a groove extending to a predetermined depth of the substrate, a non-doped silicon oxide layer provided on a whole inner surface of the groove, and a BPSG (boro-phosho-silicate glass) layer filled in a remaining portion of the groove covered with the non-doped silicon oxide layer on the inner surface. An interconnection layer is provided on the isolating region selectively.