Abstract: In a local cart traveling system, a frame track includes first and second metal rails each with an L-shaped cross section and facing each other. A local cart is within the frame track, and includes a first electricity receiving tire and a second electricity receiving tire to travel on horizontal travel surfaces of the rails. A voltage supplier supplies an AC voltage to the travel surfaces, so that the first metal rail and a first electricity receiving tire define a first capacitor and the second metal rail and the second electricity receiving tire define a second capacitor. The local cart includes a power receiver to receive AC power, and a travel motor that receives power after the AC power is rectified. The frame track includes a connecting plate as an electrical insulator covering portions of the surfaces of vertical walls of the first metal rail and the second metal rail.

Abstract: To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of the antifuse elements are at a low level, and an exclusive OR circuit that outputs different logic information for a case that the logic states are different from each other and a case that they are same as each other.

Abstract: A semiconductor device includes a plurality of first output terminals 1-13 and a plurality of first output circuits 203,204 provided corresponding to each of the plurality of first output terminals and coupled to a corresponding first output terminal. The semiconductor device further includes a second output circuit 201 coupled to a second output terminal DQS. The second output circuit automatically adjusts a slew rate based on the state transitions of the plurality of first output circuits. The second output circuit adjusts the slew rate from a first state to a second state based on a transition from first data outputted from the first output circuit to second data following said first data. The second output circuit outputs data in synchronization with the second data with a slew rate in said second state.

Abstract: Auto-refresh of a semiconductor device may be controlled by setting the number of auto-refresh to be performed in a period of time, based on temperature, when an auto-refresh command is detected.

Abstract: A control method for an air compressor including a compressor body for compressing air and an item to be replaced used during the operation of the compressor body. The method includes computing a service time of the item to be replaced, being based upon an operating time of the compressor body, discriminating whether the item to be replaced is a manufacturer's recommended item or not, determining whether or not the service time of the item to be replaced discriminated as the manufacturer's recommend item is not longer than a first reference time, but determining whether or not the service time of the item to be replaced discriminated as one which is not the manufacturer's recommended item is not longer than a preset second reference time which is shorter than the first reference time, and issuing an alarm when determining that the reference time is exceeded.

Abstract: A control method for an air compressor including a compressor body for compressing air and an item to be replaced used during the operation of the compressor body. The method includes computing a service time of the item to be replaced, being based upon an operating time of the compressor body, discriminating whether the item to be replaced is a manufacturer's recommended item or not, determining whether or not the service time of the item to be replaced discriminated as the manufacturer's recommend item is not longer than a first reference time, but determining whether or not the service time of the item to be replaced discriminated as one which is not the manufacturer's recommended item is not longer than a preset second reference time which is shorter than the first reference time, and issuing an alarm when determining that the reference time is exceeded.

Abstract: In an air compressor which can cope with an item to be replaced which is not a manufacturer's recommended item so as to enhance the safety, there is provided, as an example, an air compressor comprising a compressor body for compressing air, an item to be replaced (in detail, for example, a suction belt, a suction filter, a separator element and an oil filter) used during the operation of the compressor body, comprising a control device for computing a service time of the item to be replaced, from an operation time of the compressor body, discriminating whether the item to be replaced is a manufacturer's recommended item or not, determining whether or not the service time of the item to be replaced, which is discriminated as a manufacturer's recommended item, exceeds a preset first reference time, but determining whether the service time of the item to be replaced, which is discriminated as the one which is not the manufacturer's recommended item, exceeds a second reference time which has been preset so as to

Abstract: A semiconductor device includes a plurality of first output terminals 1-13 and a plurality of first output circuits 203,204 provided corresponding to each of the plurality of first output terminals and coupled to a corresponding first output terminal. The semiconductor device further includes a second output circuit 201 coupled to a second output terminal DQS. The second output circuit automatically adjusts a slew rate based on the state transitions of the plurality of first output circuits. The second output circuit adjusts the slew rate from a first state to a second state based on a transition from first data outputted from the first output circuit to second data following said first data. The second output circuit outputs data in synchronization with the second data with a slew rate in said second state.

Abstract: The semiconductor device includes a first pair of data lines, a second pair of data lines, a third pair of data lines, a first amplifier (SA) connected to the first pair of data lines, a first switch that controls connection between the first pair of data lines and the second pair of data lines, a second switch that controls connection between the second pair of data lines and the third pair of data lines, a second amplifier that amplifies data on the second pair of data lines, for output to the third pair of data lines, a third amplifier connected to the third pair of data lines, and a control circuit that controls the second switch forming a pair of switches. When two data lines constituting the third pair of data lines both assume a first state, the control circuit controls the second switch to be turned off, thereby controlling the second pair of data lines and the third pair of data lines to be disconnected.

Abstract: To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of the antifuse elements are at a low level, and an exclusive OR circuit that outputs different logic information for a case that the logic states are different from each other and a case that they are same as each other.

Abstract: Auto-refresh of a semiconductor device may be controlled by setting the number of auto-refresh to be performed in a period of time, based on temperature, when an auto-refresh command is detected.

Abstract: A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply line connected to a source terminal of the P-channel MOS transistor provided in each of the sense amplifiers; a second power supply line which supplies an overdrive voltage to the sense amplifiers at a potential higher than a write potential of the memory cell; a third power supply line connected to an external power supply, a connection element which connects and disconnects the first power supply line and the second power supply line; a capacitance element connected to the second power supply line; and a resistance element inserted between the second power supply line and the third power supply line.

Abstract: A semiconductor device operates in an active mode or a standby mode, and includes a substrate-potential power source line supplying a substrate potential which is higher in a standby mode than in an active mode, and a source-potential power source line supplying a source potential which is lower in a standby mode than in an active mode. During a mode shift from the standby mode to the active mode, a potential equalizing transistor is turned ON to pass a current flowing from the substrate-potential power source line to the source-potential power source line, to reduce the time length needed for shifting from the standby mode to the active mode.

Abstract: In an air compressor which can cope with an item to be replaced which is not a manufacturer's recommended item so as to enhance the safety, there is provided, as an example, an air compressor comprising a compressor body for compressing air, an item to be replaced (in detail, for example, a suction belt, a suction filter, a separator element and an oil filter) used during the operation of the compressor body, comprising a control device for computing a service time of the item to be replaced, from an operation time of the compressor body, discriminating whether the item to be replaced is a manufacturer's recommended item or not, determining whether or not the service time of the item to be replaced, which is discriminated as a manufacturer's recommended item, exceeds a preset first reference time, but determining whether the service time of the item to be replaced, which is discriminated as the one which is not the manufacturer's recommended item, exceeds a second reference time which has been preset so as to

Abstract: A semiconductor memory device includes a shared transistor controlling coupling between a bit line pair in a memory cell array and a bit line pair in a sense amplifier. After a word line is activated and the sense amplifier amplifies the potential difference between the bit lines of the bit line pair in the sense amplifier, the shared transistor is tuned OFF and precharge/equalizing circuit is activated to precharge the bit lines in the sense amplifier to a potential which is half the internal power source potential.

Abstract: A semiconductor memory device is provided that is capable of detecting a short circuit defect to be detected in a memory array without causing an error due to off-current of a sense amplifier circuit. Sense amplifier circuits amplify a potential between a pair of bit lines, which occurs based on potential of memory cells selected by driving word lines and bit lines. Selection transistors are provided between the bit lines and the sense amplifier circuits. A word-SE interval control circuit included in an X timing generating circuit turns off the selection transistors and disconnects the bit lines from the sense amplifier circuits based on a signal representing a test state for expanded time when a test to expand an interval between word line driving and activation of the sense amplifier circuits and detect defect sites of the bit lines is performed.

Abstract: A semiconductor memory device includes first and second bit lines complementary to each other, sense amplifiers, memory cells, first and second switches, an equalizer circuit, and a potential generation unit. The potential generation unit supplies a first potential to at least a selected one of the plurality of first and second bit lines through the plurality of first and second switches. The equalizer circuit sets the first and second bit lines at the second potential. When an access to the memory cell connected to the first and second bit lines, the potential generation unit gives the first potential to the second bit line.

Abstract: A complementary signal generation circuit includes a first transmission path including a first number N of inverters and a second transmission path including a second number (N?1) of inverters. A delay circuit composed of a first resistance element and a capacity element is arranged in series between two inverters in the second transmission path so as to correspond to any one of the inverters in the first transmission path. The capacity element is formed by a capacitive inverter having the same input capacity ratio as the any one of the inverters. The complementary signal generation circuit generates output signals having the logic levels which are complementary to each other through the first and second transmission paths.

Abstract: A semiconductor memory device is provided that is capable of detecting a short circuit defect to be detected in a memory array without causing an error due to off-current of a sense amplifier circuit. Sense amplifier circuits amplify a potential between a pair of bit lines, which occurs based on potential of memory cells selected by driving word lines and bit lines. Selection transistors are provided between the bit lines and the sense amplifier circuits. A word-SE interval control circuit included in an X timing generating circuit turns off the selection transistors and disconnects the bit lines from the sense amplifier circuits based on a signal representing a test state for expanded time when a test to expand an interval between word line driving and activation of the sense amplifier circuits and detect defect sites of the bit lines is performed.

Abstract: A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply line connected to a source terminal of the P-channel MOS transistor provided in each of the sense amplifiers; a second power supply line which supplies an overdrive voltage to the sense amplifiers at a potential higher than a write potential of the memory cell; a third power supply line connected to an external power supply, a connection element which connects and disconnects the first power supply line and the second power supply line; a capacitance element connected to the second power supply line; and a resistance element inserted between the second power supply line and the third power supply line.