Patents by Inventor Kazuhiro WASHIDA

Kazuhiro WASHIDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220208782
    Abstract: According to one embodiment, a semiconductor storage device includes a first stacked body, plate-shaped portions, and a wall portion. The first stacked body, in which electrically conductive layers and first insulating layers are stacked alternately one by one, includes pillar bodies that penetrate the electrically conductive layers in a stacking direction of the electrically conductive layers. The plate-shaped portions extend in a first direction intersecting the stacking direction and divide the first stacked body into blocks. The wall portion includes first and second portions. The first and second portions respectively extend in a second direction intersecting the first direction and the stacking direction and are arranged in the stacking direction. The second portion includes an outer edge connected to a side surface of the first portion and inclined with respect to the staking direction at an angle larger than an angle defined by the side surface and the stacking direction.
    Type: Application
    Filed: June 16, 2021
    Publication date: June 30, 2022
    Applicant: Kioxia Corporation
    Inventors: Kazuaki TSUNODA, Kazuhiro WASHIDA
  • Publication number: 20200251490
    Abstract: A semiconductor memory device according to an embodiment includes, a stacked portion and a pillar. The stacked portion is provided in a first region including a memory cell and in a second region. The stacked portion includes first and second conductive layers and a first insulating layer. The first conductive layers are stacked in a first direction. The second conductive layers are stacked in the first direction above the first conductive layers. The first insulating layer is provided between an uppermost first conductive layer and a lowermost second conductive layer. The pillar penetrates the first and second conductive layers and the first insulating layer.
    Type: Application
    Filed: July 26, 2019
    Publication date: August 6, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Sota MATSUMOTO, Junichi SHIBATA, Takahito NISHIMURA, Kazuhiro WASHIDA