Patents by Inventor Kazuhisa Fujimoto
Kazuhisa Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11366695Abstract: A charging assistant system that assists charging for use of an accelerator unit, which is one or more accelerators, includes an operation amount obtaining unit, an acceleration rate estimation unit, and a use fee determination unit. For each of one or more commands input into the accelerator unit, the operation amount obtaining unit obtains the amount of operation related to execution of the command from a response output from the accelerator unit for the command. For the one or more commands input into the accelerator unit, the acceleration rate estimation unit estimates an acceleration rate on the basis of command execution time that is time required for processing of the one or more commands, and one or more amounts of operation obtained for the one or more commands respectively. The use fee determination unit determines a use fee of the accelerator unit on the basis of the estimated acceleration rate.Type: GrantFiled: September 7, 2018Date of Patent: June 21, 2022Assignee: HITACHI, LTD.Inventors: Yoshifumi Fujikawa, Kazuhisa Fujimoto, Toshiyuki Aritsuka, Kazushi Nakagawa
-
Patent number: 11151141Abstract: It is possible execute processing large-scale data and improve the processing efficiency while suppressing the complexity of a hardware circuit. A data processing device includes a processor and a FPGA connected to the processor. The processor is configured to acquire a query plan including target identification information identifying data to be processed and a processing detail for the data to be processed, generate, based on the query plan, a plurality of FPGA commands to process a plurality of row group data items constituting the data identified by the target identification information and to be processed, and transmit the FPGA commands to the FPGA. The FPGA is configured to execute processing on the row group data items based on the transmitted FPGA commands and return results of executing the processing to the processor.Type: GrantFiled: August 23, 2019Date of Patent: October 19, 2021Assignee: HITACHI, LTD.Inventors: Yoshifumi Fujikawa, Toshiyuki Aritsuka, Satoru Watanabe, Kazushi Nakagawa, Kazuhisa Fujimoto, Masahiro Arai
-
Patent number: 11150829Abstract: A storage system and data control method capable of extending the service lifes of storage devices of the same type and with different properties and reducing operation management cost are proposed. The storage system includes: a first storage device; a second storage device with a smaller upper limit number of writes and a larger storage capacity per unit area than those of the first storage device; and a processor that allocates storage areas from the first storage device and the second storage device to a virtual volume to be provided to a host, wherein the processor relocates data which is stored in a storage area with higher write frequency from the host than a predetermined write threshold, from among the storage areas allocated from the second storage device to the virtual volume, from the storage area of the second storage device to a storage area of the first storage device.Type: GrantFiled: October 7, 2019Date of Patent: October 19, 2021Assignee: HITACHI, LTD.Inventors: Takahiro Yamamoto, Kazuhisa Fujimoto, Hiroaki Akutsu
-
Patent number: 10936377Abstract: The data processing times of data processing nodes are heterogeneous, and hence the execution time of a whole system is not optimized. A task is executed using a plurality of optimal computing devices by distributing a data amount of data to be processed with a processing command of the task for the plurality of optimal computing devices depending on a difference in computing power between the plurality of optimal computing devices, to thereby execute the task in a distributed manner using the plurality of optimal computing devices.Type: GrantFiled: February 28, 2017Date of Patent: March 2, 2021Assignee: HITACHI, LTD.Inventors: Toshiyuki Aritsuka, Kazushi Nakagawa, Kazuhisa Fujimoto
-
Patent number: 10789253Abstract: A storage device, connected to a computer including a processor and first memory, and executing a program, stores data processed under the program. The computer includes a protocol processing unit that accesses data in the storage device, an accelerator that includes an arithmetic unit executing a part of a process of the program, and a second memory storing data, and executes the part of the process. The first memory receives a processing request for processing data, and causes the accelerator to execute a command to process data, corresponding to the processing request for the processing request including a process to be executed by the arithmetic unit. The accelerator requests the protocol processing unit to provide target data indicated by a command received from the program, reads data from the storage device via the protocol processing unit, and stores the data in the second memory. The arithmetic unit executes the command.Type: GrantFiled: April 27, 2016Date of Patent: September 29, 2020Assignee: Hitachi, Ltd.Inventors: Kazuhisa Fujimoto, Shinji Fujiwara, Satoru Watanabe, Akira Yamamoto
-
Publication number: 20200265052Abstract: It is possible execute processing large-scale data and improve the processing efficiency while suppressing the complexity of a hardware circuit. A data processing device includes a processor and a FPGA connected to the processor. The processor is configured to acquire a query plan including target identification information identifying data to be processed and a processing detail for the data to be processed, generate, based on the query plan, a plurality of FPGA commands to process a plurality of row group data items constituting the data identified by the target identification information and to be processed, and transmit the FPGA commands to the FPGA. The FPGA is configured to execute processing on the row group data items based on the transmitted FPGA commands and return results of executing the processing to the processor.Type: ApplicationFiled: August 23, 2019Publication date: August 20, 2020Applicant: HITACHI, LTD.Inventors: Yoshifumi Fujikawa, Toshiyuki Aritsuka, Satoru Watanabe, Kazushi Nakagawa, Kazuhisa Fujimoto, Masahiro Arai
-
Publication number: 20200034067Abstract: A storage system and data control method capable of extending the service lifes of storage devices of the same type and with different properties and reducing operation management cost are proposed. The storage system includes: a first storage device; a second storage device with a smaller upper limit number of writes and a larger storage capacity per unit area than those of the first storage device; and a processor that allocates storage areas from the first storage device and the second storage device to a virtual volume to be provided to a host, wherein the processor relocates data which is stored in a storage area with higher write frequency from the host than a predetermined write threshold, from among the storage areas allocated from the second storage device to the virtual volume, from the storage area of the second storage device to a storage area of the first storage device.Type: ApplicationFiled: October 7, 2019Publication date: January 30, 2020Applicant: HITACHI, LTD.Inventors: Takahiro YAMAMOTO, Kazuhisa FUJIMOTO, Hiroaki AKUTSU
-
Publication number: 20190324969Abstract: A storage device, connected to a computer including a processor and first memory, and executing a program, stores data processed under the program. The computer includes a protocol processing unit that accesses data in the storage device, an accelerator that includes an arithmetic unit executing a part of a process of the program, and a second memory storing data, and executes the part of the process. The first memory receives a processing request for processing data, and causes the accelerator to execute a command to process data, corresponding to the processing request for the processing request including a process to be executed by the arithmetic unit. The accelerator requests the protocol processing unit to provide target data indicated by a command received from the program, reads data from the storage device via the protocol processing unit, and stores the data in the second memory. The arithmetic unit executes the command.Type: ApplicationFiled: April 27, 2016Publication date: October 24, 2019Inventors: Kazuhisa FUJIMOTO, Shinji FUJIWARA, Satoru WATANABE, Akira YAMAMOTO
-
Patent number: 10452302Abstract: A storage system and data control method capable of extending the service lifes of storage devices of the same type and with different properties and reducing operation management cost are proposed. The storage system includes: a first storage device; a second storage device with a smaller upper limit number of writes and a larger storage capacity per unit area than those of the first storage device; and a processor that allocates storage areas from the first storage device and the second storage device to a virtual volume to be provided to a host, wherein the processor relocates data which is stored in a storage area with higher write frequency from the host than a predetermined write threshold, from among the storage areas allocated from the second storage device to the virtual volume, from the storage area of the second storage device to a storage area of the first storage device.Type: GrantFiled: April 9, 2015Date of Patent: October 22, 2019Assignee: HITACHI, LTD.Inventors: Takahiro Yamamoto, Kazuhisa Fujimoto, Hiroaki Akutsu
-
Publication number: 20190272201Abstract: The data processing times of data processing nodes are heterogeneous, and hence the execution time of a whole system is not optimized. A task is executed using a plurality of optimal computing devices by distributing a data amount of data to be processed with a processing command of the task for the plurality of optimal computing devices depending on a difference in computing power between the plurality of optimal computing devices, to thereby execute the task in a distributed manner using the plurality of optimal computing devices.Type: ApplicationFiled: February 28, 2017Publication date: September 5, 2019Applicant: HITACHI, LTD.Inventors: Toshiyuki ARITSUKA, Kazushi NAKAGAWA, Kazuhisa FUJIMOTO
-
Publication number: 20190228009Abstract: An accelerator is mounted on each server which is a worker node of a distributed DB system; a query generated by an application of an application server is divided into a first task that should be executed by the accelerator and a second task that should be executed by software and is allocated to the server of the distributed DB system; the server causes the accelerator to execute the first task, and executes the second task based on the software.Type: ApplicationFiled: February 2, 2018Publication date: July 25, 2019Applicant: HITACHI, LTD.Inventors: Kazushi NAKAGAWA, Toshiyuki ARITSUKA, Kazuhisa FUJIMOTO, Satoru WATANABE, Yoshifumi FUJIKAWA
-
Publication number: 20190196746Abstract: An information processing device and a method having high processing performance are proposed. Provided is an information processing device mounted with an accelerator that executes predetermined processing on data, the information processing device including: a storage device configured to store data; and a host control unit configured to request the accelerator to execute the predetermined processing included in a task requested from an outside, in which the data is compressed and stored in the storage device, and in which the accelerator: reads the data to be processed among the data stored in the storage device and executes the predetermined processing on the data while decompressing the read data in response to a request from the host control unit.Type: ApplicationFiled: March 30, 2017Publication date: June 27, 2019Inventors: Kazuhisa FUJIMOTO, Koji HOSOGI, Toshiyuki ARITSUKA, Kazushi NAKAGAWA
-
Publication number: 20190129755Abstract: A charging assistant system that assists charging for use of an accelerator unit, which is one or more accelerators, includes an operation amount obtaining unit, an acceleration rate estimation unit, and a use fee determination unit. For each of one or more commands input into the accelerator unit, the operation amount obtaining unit obtains the amount of operation related to execution of the command from a response output from the accelerator unit for the command. For the one or more commands input into the accelerator unit, the acceleration rate estimation unit estimates an acceleration rate on the basis of command execution time that is time required for processing of the one or more commands, and one or more amounts of operation obtained for the one or more commands respectively. The use fee determination unit determines a use fee of the accelerator unit on the basis of the estimated acceleration rate.Type: ApplicationFiled: September 7, 2018Publication date: May 2, 2019Applicant: HITACHI, LTD.Inventors: Yoshifumi FUJIKAWA, Kazuhisa FUJIMOTO, Toshiyuki ARITSUKA, Kazushi NAKAGAWA
-
Patent number: 10241909Abstract: A write frequency of a non-volatile memory is determined at a fine granularity while suppressing consumption of the volatile memory. When it is determined that a copy of specified data from a specified physical storage area to another physical storage area is to be executed, a controller reads the specified data and specified write frequency information, selects a write destination physical storage area group from a plurality of physical storage area groups based on the specified write frequency information and classification information, selects a write destination physical storage area from the write destination physical storage area group, changes the specified write frequency information, writes the specified data to the write destination physical storage area, writes the changed specified write frequency information to the non-volatile memory, and updates translation information based on the write destination physical storage area group and the write destination physical storage area.Type: GrantFiled: February 27, 2015Date of Patent: March 26, 2019Assignee: Hitachi, Ltd.Inventors: Atsushi Kawamura, Masahiro Arai, Kazuhisa Fujimoto
-
Publication number: 20180067850Abstract: A write frequency of a non-volatile memory is determined at a fine granularity while suppressing consumption of the volatile memory. When it is determined that a copy of specified data from a specified physical storage area to another physical storage area is to be executed, a controller reads the specified data and specified write frequency information, selects a write destination physical storage area group from a plurality of physical storage area groups based on the specified write frequency information and classification information, selects a write destination physical storage area from the write destination physical storage area group, changes the specified write frequency information, writes the specified data to the write destination physical storage area, writes the changed specified write frequency information to the non-volatile memory, and updates translation information based on the write destination physical storage area group and the write destination physical storage area.Type: ApplicationFiled: February 27, 2015Publication date: March 8, 2018Applicant: HITACHI, LTD.Inventors: Atsushi KAWAMURA, Masahiro ARAI, Kazuhisa FUJIMOTO
-
Publication number: 20180039444Abstract: A storage system and data control method capable of extending the service lifes of storage devices of the same type and with different properties and reducing operation management cost are proposed. The storage system includes: a first storage device; a second storage device with a smaller upper limit number of writes and a larger storage capacity per unit area than those of the first storage device; and a processor that allocates storage areas from the first storage device and the second storage device to a virtual volume to be provided to a host, wherein the processor relocates data which is stored in a storage area with higher write frequency from the host than a predetermined write threshold, from among the storage areas allocated from the second storage device to the virtual volume, from the storage area of the second storage device to a storage area of the first storage device.Type: ApplicationFiled: April 9, 2015Publication date: February 8, 2018Applicant: HITACHI, LTD.Inventors: Takahiro YAMAMOTO, Kazuhisa FUJIMOTO, Hiroaki AKUTSU
-
Publication number: 20170286507Abstract: A database search system receives a command and searches for data, which meets a search condition specified on the basis of the received command, in a whole database which is a database as an entity. The database search system generates a virtual database which is a list of address pointers to the found data and stores the generated virtual database.Type: ApplicationFiled: July 22, 2015Publication date: October 5, 2017Applicant: Hitachi, Ltd.Inventors: Koji HOSOGI, Mitsuhiro OKADA, Akifumi SUZUKI, Shimpei NOMURA, Kazuhisa FUJIMOTO, Satoru WATANABE, Yoshiki KUROKAWA, Yoshitaka TSUJIMOTO
-
Patent number: 9495105Abstract: A system includes a plurality of flash memory devices, a processor configured to control read/write requests, and a cache memory configured to store data temporarily.Type: GrantFiled: January 7, 2016Date of Patent: November 15, 2016Assignee: Hitachi, Ltd.Inventors: Shuji Nakamura, Kazuhisa Fujimoto, Akira Fujibayashi
-
Publication number: 20160179380Abstract: A system includes a plurality of flash memory devices, a processor configured to control read/write requests, and a cache memory configured to store data temporarily.Type: ApplicationFiled: January 7, 2016Publication date: June 23, 2016Inventors: Shuji NAKAMURA, Kazuhisa FUJIMOTO, Akira FUJIBAYASHI
-
Patent number: 9251063Abstract: A storage system including a storage device which includes media for storing data from a host computer, a medium controller for controlling the media, a plurality of channel controllers for connecting to the host computer through a channel and a cache memory for temporarily storing data from the host computer, wherein the media have a restriction on a number of writing times. The storage device includes a bus for directly transferring data from the medium controller to the channel controller.Type: GrantFiled: December 6, 2013Date of Patent: February 2, 2016Assignee: Hitachi, Ltd.Inventors: Shuji Nakamura, Kazuhisa Fujimoto, Akira Fujibayashi