Patents by Inventor Kazuhisa Hasumi

Kazuhisa Hasumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11713963
    Abstract: Line-edge roughness or line width roughness is evaluated while preventing influence of noise caused by a device or an environment. Therefore, an averaged signal profile 405 in which a moving average of S pixels (S is an integer greater than 1) is taken in a Y direction is obtained from a signal profile showing a secondary electron signal amount distribution in an X direction with respect to a predetermined Y coordinate obtained from a top-down image, an edge position 406 of a line pattern is extracted based on the averaged signal profile, and a noise floor height is calculated based on a first power spectral density 407 of LER data or LWR data based on the extracted edge position and a second power spectral density 409 of a rectangular window function corresponding to the moving average of the S pixels.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: August 1, 2023
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Atsuko Shintani, Takahiro Kawasaki, Kazuhisa Hasumi, Masami Ikota, Hiroki Kawada
  • Patent number: 11430106
    Abstract: An object of the invention is to quantitatively evaluate crystal growth amount in a wide range from an undergrowth state to an overgrowth state with nondestructive inspection. By using a plenty of image feature values such as pattern brightness, a pattern area and a pattern shape which are extracted from an SEM image, and depending on whether brightness inside a pattern is lower than brightness outside the pattern (401), undergrowth and overgrowth is determined (402, 405). Based on a brightness difference or the pattern area, a growth amount index or a normality index of crystal growth in a concave pattern such as a hole pattern or a trench pattern is calculated (404, 407).
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: August 30, 2022
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Takeyoshi Ohashi, Atsuko Shintani, Masami Ikota, Kazuhisa Hasumi
  • Publication number: 20220034653
    Abstract: Line-edge roughness or line width roughness is evaluated while preventing influence of noise caused by a device or an environment. Therefore, an averaged signal profile 405 in which a moving average of S pixels (S is an integer greater than 1) is taken in a Y direction is obtained from a signal profile showing a secondary electron signal amount distribution in an X direction with respect to a predetermined Y coordinate obtained from a top-down image, an edge position 406 of a line pattern is extracted based on the averaged signal profile, and a noise floor height is calculated based on a first power spectral density 407 of LER data or LWR data based on the extracted edge position and a second power spectral density 409 of a rectangular window function corresponding to the moving average of the S pixels.
    Type: Application
    Filed: May 29, 2019
    Publication date: February 3, 2022
    Inventors: Atsuko Shintani, Takahiro Kawasaki, Kazuhisa Hasumi, Masami Ikota, Hiroki Kawada
  • Patent number: 10854420
    Abstract: A pattern evaluation device has measurement or inspection conditions, supplied for the measurement and inspection of a replica produced by transferring a pattern for a semiconductor wafer or the like, which can be easily set, and with which recipes can be easily generated, when measurement and inspection conditions for the semiconductor wafer or the like and recipes in which these conditions are stored have been prepared in advance. The pattern evaluation device in which a pattern formed on the semiconductor wafer is evaluated on the basis of image data or signal waveforms obtained on the basis of beam irradiation or probe scanning of the semiconductor wafer, wherein the device conditions for evaluating the semiconductor wafer are converted to device conditions for evaluating a replica obtained by transferring a part of a pattern of the semiconductor wafer, and the converted device conditions are used to evaluate the replica.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: December 1, 2020
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Miki Isawa, Ayumi Doi, Kazuhisa Hasumi
  • Patent number: 10724856
    Abstract: To provide an image analysis apparatus capable of easily extracting an edge of an upper layer pattern formed intersecting with a lower layer pattern so as not to be affected by the lower layer pattern, the image analysis apparatus includes a calculation unit that calculates an analysis range including a region where the lower layer pattern intersects with the upper layer pattern and a region where the lower pattern is not formed, a calculation unit that averages a plurality of signal profiles, a calculation unit that calculates a maximum value and a minimum value of a signal intensity, a calculation unit that calculates a threshold level difference using the maximum value and the minimum value, and a calculation unit that calculates the edge of the upper layer pattern on the signal profile.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: July 28, 2020
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Atsuko Yamaguchi, Kazuhisa Hasumi, Hitoshi Namai
  • Publication number: 20200219243
    Abstract: An object of the invention is to quantitatively evaluate crystal growth amount in a wide range from an undergrowth state to an overgrowth state with nondestructive inspection. By using a plenty of image feature values such as pattern brightness, a pattern area and a pattern shape which are extracted from an SEM image, and depending on whether brightness inside a pattern is lower than brightness outside the pattern (401), undergrowth and overgrowth is determined (402, 405). Based on a brightness difference or the pattern area, a growth amount index or a normality index of crystal growth in a concave pattern such as a hole pattern or a trench pattern is calculated (404, 407).
    Type: Application
    Filed: August 23, 2017
    Publication date: July 9, 2020
    Inventors: Takeyoshi OHASHI, Atsuko SHINTANI, Masami IKOTA, Kazuhisa HASUMI
  • Patent number: 10672119
    Abstract: In order to provide an inspection device capable of quantitatively evaluating a pattern related to a state of a manufacturing process or performance of an element, it is assumed that an inspection device includes an image analyzing unit that analyzes a top-down image of a sample in which columnar patterns are formed at a regular interval, in which an image analyzing unit 240 includes a calculation unit 243 that obtains a major axis, a minor axis, an eccentricity, and an angle formed by a major axis direction with an image horizontal axis direction of the approximated ellipse as a first index and a Cr calculation unit 248 that obtains a circumferential length of an outline of a columnar pattern on the sample and a value obtained by dividing a square of the circumferential length by a value obtained by multiplying an area surrounded by the outline and 4? as a second index.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: June 2, 2020
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Atsuko Yamaguchi, Masami Ikota, Kazuhisa Hasumi
  • Publication number: 20200098543
    Abstract: Provided is a pattern evaluation device with which measurement or inspection conditions, supplied for the measurement and inspection of a replica produced by transferring a pattern for a semiconductor wafer or the like, can be easily set, and with which recipes can be easily generated, when measurement and inspection conditions for a semiconductor wafer or the like and recipes in which these conditions are stored have been prepared in advance. The pattern evaluation device in which a pattern formed on a sample is evaluated on the basis of image data or signal waveforms obtained on the basis of beam irradiation or probe scanning of the sample, wherein the device conditions for evaluating a semiconductor wafer are converted to device conditions for evaluating a replica obtained by transferring a semiconductor wafer, and the converted device conditions are used to evaluate the replica.
    Type: Application
    Filed: July 22, 2016
    Publication date: March 26, 2020
    Inventors: Miki ISAWA, Ayumi DOI, Kazuhisa HASUMI
  • Publication number: 20190204247
    Abstract: To provide an image analysis apparatus capable of easily extracting an edge of an upper layer pattern formed intersecting with a lower layer pattern so as not to be affected by the lower layer pattern, the image analysis apparatus includes a calculation unit that calculates an analysis range including a region where the lower layer pattern intersects with the upper layer pattern and a region where the lower pattern is not formed, a calculation unit that averages a plurality of signal profiles, a calculation unit that calculates a maximum value and a minimum value of a signal intensity, a calculation unit that calculates a threshold level difference using the maximum value and the minimum value, and a calculation unit that calculates the edge of the upper layer pattern on the signal profile.
    Type: Application
    Filed: September 1, 2016
    Publication date: July 4, 2019
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Atsuko YAMAGUCHI, Kazuhisa HASUMI, Hitoshi NAMAI
  • Patent number: 10295339
    Abstract: A pattern measurement method and measurement apparatus are provided that appropriately evaluate the deformation of a pattern occurring due to a micro loading effect. In order to achieve the above-mentioned object, there are provided pattern measurement method and apparatus that measure a dimension of a pattern formed on a sample. In the pattern measurement method and apparatus, distances between a reference pattern and a plurality of adjacent patterns adjacent to the reference pattern or inner diameters of the reference pattern in a plurality of directions are measured, and the measurement results of the plurality of distances between the reference pattern and the adjacent patterns or the measurement results of the inner diameters of the reference pattern in the plurality of directions are classified according to distances between the reference pattern and the adjacent patterns or directions of the patterns adjacent to the reference pattern.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: May 21, 2019
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Kazuhisa Hasumi, Masami Ikota
  • Publication number: 20180308228
    Abstract: In order to provide an inspection device capable of quantitatively evaluating a pattern related to a state of a manufacturing process or performance of an element, it is assumed that an inspection device includes an image analyzing unit that analyzes a top-down image of a sample in which columnar patterns are formed at a regular interval, in which an image analyzing unit 240 includes a calculation unit 243 that obtains a major axis, a minor axis, an eccentricity, and an angle formed by a major axis direction with an image horizontal axis direction of the approximated ellipse as a first index and a Cr calculation unit 248 that obtains a circumferential length of an outline of a columnar pattern on the sample and a value obtained by dividing a square of the circumferential length by a value obtained by multiplying an area surrounded by the outline and 4? as a second index.
    Type: Application
    Filed: September 10, 2015
    Publication date: October 25, 2018
    Inventors: Atsuko YAMAGUCHI, Masami IKOTA, Kazuhisa HASUMI
  • Patent number: 9831062
    Abstract: An object of the present invention is to provide a method for pattern measurement and a charged particle radiation device in which a pattern formed by using a DSA technique can be very precisely measured and inspected. According to an aspect for achieving the object, a method for pattern measurement or a charged particle radiation device for realizing the measurement is proposed as follows. A charged particle is radiated to a polymer compound used for a self-organization lithography technique, and a specific polymer is considerably contracted as compared to the other polymer among multiple polymers forming the polymer compound. Thereafter, dimensions between multiple edges of the other polymer are measured, based on a signal obtained by scanning a region including the other polymer with the charged particle beam.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: November 28, 2017
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Makoto Suzuki, Satoru Yamaguchi, Kei Sakai, Miki Isawa, Satoshi Takada, Kazuhisa Hasumi, Masami Ikota
  • Publication number: 20170030712
    Abstract: A pattern measurement method and measurement apparatus are provided that appropriately evaluate the deformation of a pattern occurring due to a micro loading effect. In order to achieve the above-mentioned object, there are provided pattern measurement method and apparatus that measure a dimension of a pattern formed on a sample. In the pattern measurement method and apparatus, distances between a reference pattern and a plurality of adjacent patterns adjacent to the reference pattern or inner diameters of the reference pattern in a plurality of directions are measured, and the measurement results of the plurality of distances between the reference pattern and the adjacent patterns or the measurement results of the inner diameters of the reference pattern in the plurality of directions are classified according to distances between the reference pattern and the adjacent patterns or directions of the patterns adjacent to the reference pattern.
    Type: Application
    Filed: July 21, 2016
    Publication date: February 2, 2017
    Inventors: Kazuhisa HASUMI, Masami IKOTA
  • Publication number: 20150357158
    Abstract: An object of the present invention is to provide a method for pattern measurement and a charged particle radiation device in which a pattern formed by using a DSA technique can be very precisely measured and inspected. According to an aspect for achieving the object, a method for pattern measurement or a charged particle radiation device for realizing the measurement is proposed as follows. A charged particle is radiated to a polymer compound used for a self-organization lithography technique, and a specific polymer is considerably contracted as compared to the other polymer among multiple polymers forming the polymer compound. Thereafter, dimensions between multiple edges of the other polymer are measured, based on a signal obtained by scanning a region including the other polymer with the charged particle beam.
    Type: Application
    Filed: January 22, 2014
    Publication date: December 10, 2015
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Makoto SUZUKI, Satoru YAMAGUCHI, Kei SAKAI, Miki ISAWA, Satoshi TAKADA, Kazuhisa HASUMI, Masami IKOTA
  • Publication number: 20140177940
    Abstract: A desired area is extracted by directly analyzing information recorded in a design layout, an inspection recipe is generated by using this extraction method, and an efficient inspection is realized. The invention makes it easy to extract an area of a desired circuit module such as a memory mat by analyzing hierarchy information of design layout data, calculating reference frequency of each one cell in the design layout data that is its internal data, sorting the cells in order of increasing reference frequency, searching the object, and tracing its upper cell.
    Type: Application
    Filed: May 28, 2011
    Publication date: June 26, 2014
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Ryo Nakagaki, Yuichi Hamamura, Yuji Enomoto, Yutaka Tandai, Tsunehiro Sakai, Kazuhisa Hasumi
  • Patent number: 8670115
    Abstract: The inspection conditions of a known inspection apparatus necessary for inspection are such that wafers are individually prepared for respective layer types and layer thicknesses, and standard particles having different sizes are applied to all of the wafers. Moreover, the wafers to which standard particles have been applied and which have been prepared for the respective layer types and layer thicknesses are inspected by the inspection apparatus to determine the optimal inspection conditions for the respective layer types and layer thicknesses. Therefore, there are problems that it requires long time and involves high cost to determine the inspection conditions. In the invention, the relation between the layer thickness and the scattering intensity in the inspection apparatus is calculated. The scattering intensity is divided into a plurality of intensity regions, and the inspection conditions optimized for the respective divided regions are determined.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: March 11, 2014
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yuji Miyoshi, Kazuhisa Hasumi
  • Patent number: 8595666
    Abstract: A defect is efficiently and effectively classified by accurately determining the state of overlap between a design layout pattern and the defect. This leads to simple identification of a systematic defect. A defective image obtained through defect inspection or review of a semiconductor device is automatically pattern-matched with design layout data. A defect is superimposed on a design layout pattern for at least one layer of a target layer, a layer immediately above the target layer, and a layer immediately below the target layer. The state of overlap of the defect is determined as within the pattern, over the pattern, or outside the pattern, and the defect is automatically classified.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: November 26, 2013
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Koichi Hayakawa, Takehiro Hirai, Yutaka Tandai, Tamao Ishikawa, Tsunehiro Sakai, Kazuhisa Hasumi, Kazunori Nemoto, Katsuhiko Ichinose, Yuji Takagi
  • Publication number: 20120131529
    Abstract: A defect is efficiently and effectively classified by accurately determining the state of overlap between a design layout pattern and the defect. This leads to simple identification of a systematic defect. A defective image obtained through defect inspection or review of a semiconductor device is automatically pattern-matched with design layout data. A defect is superimposed on a design layout pattern for at least one layer of a target layer, a layer immediately above the target layer, and a layer immediately below the target layer. The state of overlap of the defect is determined as within the pattern, over the pattern, or outside the pattern, and the defect is automatically classified.
    Type: Application
    Filed: May 14, 2010
    Publication date: May 24, 2012
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Koichi Hayakawa, Takehiro Hirai, Yutaka Tandai, Tamao Ishikawa, Tsunehiro Sakai, Kazuhisa Hasumi, Kazunori Nemoto, Katsuhiko Ichinose, Yuji Takagi
  • Publication number: 20110255080
    Abstract: The inspection conditions of a known inspection apparatus necessary for inspection are such that wafers are individually prepared for respective layer types and layer thicknesses, and standard particles having different sizes are applied to all of the wafers. Moreover, the wafers to which standard particles have been applied and which have been prepared for the respective layer types and layer thicknesses are inspected by the inspection apparatus to determine the optimal inspection conditions for the respective layer types and layer thicknesses. Therefore, there are problems that it requires long time and involves high cost to determine the inspection conditions. In the invention, the relation between the layer thickness and the scattering intensity in the inspection apparatus is calculated. The scattering intensity is divided into a plurality of intensity regions, and the inspection conditions optimized for the respective divided regions are determined.
    Type: Application
    Filed: December 14, 2009
    Publication date: October 20, 2011
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Yuji Miyoshi, Kazuhisa Hasumi
  • Patent number: 6087924
    Abstract: In a gas sensor which uses CuO as a p-type semiconductor, by adding Na.sub.2 CO.sub.3 in excess of 1 wt % relative to CuO, sensitivity to gases such as H.sub.2, NO, NO.sub.2 and SO.sub.2 is suppressed, whereby selectivity for CO is increased. Sensitivity to CO.sub.2 can also be obtained. In addition, by adding a sodium salt of tungstic acid or molybdic acid, CO.sub.2 sensitivity can be made lower than the CO sensitivity, and CO gas in the exhaust gases discharged from gas-fired water heaters or other combustion equipment can be selectively detected. It is therefore possible to detect incomplete combustion.
    Type: Grant
    Filed: December 15, 1997
    Date of Patent: July 11, 2000
    Assignees: Mikuni Corporation, Osaka Gas Co., Ltd.
    Inventors: Kazuhisa Hasumi, Kentaro Nagano, Hideyuki Horiuchi, Osamu Okada