Abstract: An idling current setting circuit (3) includes: current setting transistors (Q3, Q4) connected to output transistors (Q1, Q2) in a driver (2) in current mirror form; a plurality of current setting resistors (R1 to R4); and a plurality of switches (ASW1 to ASW4) for switching to any of the current setting resistors (R1 to R4). This enables the idling current to be set by the current mirror ratio between the current setting transistors (Q3, Q4) having no connection with the open gain of the power amplifier and the output transistors (Q1, Q2), so that the idling current can be arbitrarily set independently of the open gain.

Abstract: There are provided a frequency converting circuit 21 for inputting a broadband IF signal which includes a disturbing wave and carrying out a frequency conversion with an oscillating signal having a frequency of a desirable wave, and outputting a signal including a sum frequency component of a frequency component of a disturbing wave which is included in the IF signal and a frequency component of a desirable wave of the oscillating signal and a difference frequency component therebetween, and a low-pass filter 22 for attenuating the sum frequency component to output a signal of the difference frequency component, and a presence of an intermodulation disturbance is detected based on a frequency relationship between two difference frequency components output from the low-pass filter 22.

Abstract: A first MOS transistor (M1) and a second MOS transistor (M2) constitute a cascode amplifier. The second MOS transistor (M2) is in a differential connection with a gain control MOS transistor (M4), which has its gate supplied with an AGC control voltage (VAGC), and it is arranged that the device area ratio of the second MOS transistor (M2) to the gain control MOS transistor (M4) is one to N (where N?1). In this way, even in a region where the AGC control voltage (VAGC) is small, abrupt variations of the gain can be suppressed, while the drain current of the first MOS transistor (M1) can be kept constant independently of the gain control.

Abstract: By connecting an antenna damping circuit (4) and a bypass switch (5) in series and connecting the series circuit and an LNA (3) in parallel, it is possible to inhibit a generation of a signal path for connecting the bypass switch (5) to the LNA (3) in series in an operation of the LNA (3) and to prevent a noise factor of the LNA (3) from being deteriorated due to an on resistance of the bypass switch (5).

Abstract: The present invention provides a variable gain amplifier including a plurality of initial-stage LNAs 1 to 4 connected parallel to one input terminal IN, a next-stage LNA 5 connected after the initial-stage LNAs 1 to 4 and a variable current source 20 that performs control such that a total value of initial-stage control currents IB1 to IB4 simultaneously flowing through the initial-stage LNAs 1 to 4 is kept constant and such that-next-stage control currents IB13 and IB24 of magnitude proportional to the initial-stage control currents IB1 to IB4 which are let flow through the initial-stage LNAs 1 to 4 are let flow through the next-stage LNA 5, wherein the necessity for causing an excessively large fixed current to flow through the next-stage LNA 5 is eliminated and the next-stage control currents IB13 and IB24 are reduced to a minimum necessary magnitude so that increases of useless current consumption can be suppressed.

Abstract: An antenna damping circuit in which the frequency characteristics of damping amount can be made substantially flat by providing a resistor (Ra) between PIN diodes (D1, D2) having a resistance varying upon application of a control voltage (Vc) and a capacitive dummy antenna circuit (10), and setting its resistance high enough to neglect the capacity of the dummy antenna circuit (10) sufficiently when the dummy antenna circuit (10) is viewed from the side of the PIN diodes (D1, D2) thereby substantially eliminating the influence of capacity of the dummy antenna circuit (10).

Abstract: An arbitrary threshold value (Ei0) is established which defines a boundary as to activating an RF-AGC circuit (21) if the value of the field intensity (Ei) of a received signal is greater than what value while the value of the field intensity of a signal at a desired frequency being a predetermined value (Ei0) in a weak field area. The established value (Ei0) is used to provide a threshold value establishing/controlling part (22) that controls the ON/OFF of the operation of the RF-AGC circuit (21). In this way, a set maker or the like of an IC including an automatic gain control part (11) can perform a field test or the like such that a preferable value obtained by a result of the field test or the like can be used as an AGC start level (Ei0), whereby an optimum AGC control can be performed based on the preferable AGC start level (Ei0).

Abstract: This invention includes a gain control section 13 capable of changing an APC loop gain according to a power output level set in a power amplifier to allow suppression of variation in power output level when the power output level is low and suppression of occurrence of ringing when the power output level is high by making the loop gain high when the power output level is low and making the loop gain low when the power output level is high.

Abstract: A received spread spectrum signal is despread by a first despreading circuit, and according to this first despread signal, a synchronizing signal generator (PLL) generates a signal in phase with the first despread signal. According to the output signal from the synchronizing signal generator, a spreading code generator generates a plurality of Spreading codes out of phase with one another. The plurality of spreading codes are supplied to a second despreading circuit, which despreads the received spread spectrum signal by the plurality of spreading codes, and thus, a plurality of second despread signals are obtained. A correlation detector detects the correlation between the spread spectrum signal and each of the plurality of spreading codes on the basis of the plurality of second despread signals. According to the correlation results, a control circuit determines the direction in which to shift the phase of the plurality of spreading codes with respect to the received spread spectrum signal.

Abstract: In a spread spectrum signal receiver, a frequency divider circuit divides the frequency of the output signal of a VCO having a phase synchronized with that of the output signal of first multiplier. A first spreading code generating circuit generates a spreading code in response to the output signal of the frequency divider circuit. A second spreading code generating circuit generates first through third spreading codes in response to the spreading code. A selection circuit selects one of the first through third spreading codes. A second multiplier despreads the spectrum using the spreading code output from the selection circuit. A correlation detector circuit detects correlation from the output signal of the second multiplier and a control signal generates a delay or advance control signal in response to the detected correlation. The frequency dividing ratio of the frequency divider circuit is switched according to the delay or advance control signal.

Abstract: An amplifier circuit includes a negative feedback connected amplifier and a series circuit comprising a capacitor, one end of which is connected to an output terminal of the amplifier, and a resistor, one end of which is connectable to a reference potential. A comparator is provided which has first and second inputs and one output. The first input is connected to a junction between the capacitor and the resistor, the second input is connected to an output of the amplifier, and the output of the comparator is connected to one input of the amplifier. The comparator does not react to an AC signal of a specific frequency band, but operates to set the output offset voltage only to one fractional part of the transition gain, and therefore operates to accomplish offset compensation without using a large capacitor.

Abstract: A FSK data signal voltage inputted from an input terminal 4 is converted into current by a resistance R.sub.1 and then the current is differentially amplified with respect to a reference voltage of a capacitor C.sub.1 in a second differential amplifier circuit 2. As a result, a waveform-shaped signal is generated from each collector of transistors Q.sub.2 and Q.sub.3 constituting the second differential amplifier circuit 2. Meanwhile, the FSK data signal inputted from the input terminal 4, after an alternating current signal component thereof is removed, is applied to a third differential amplifier circuit 3 wherein a difference between the signal and the reference voltage of the capacitor C.sub.1 is amplified. Charging/discharging the capacitor C.sub.1 is controlled in response to an output of the third differential amplifier circuit 3.

Abstract: An amplification circuit including a differential amplifier is disclosed. An npn transistor portion of the differential amplifier has its base provided with negative feed back, the base potential is brought to a constant potential, i.e. a virtual ground potential. The voltage between the base and emitter of the transistor is thus kept constant, and the internal resistance of the emitter does not change in accordance with the change of the emitter current. As a result, since the transistor responds only to an input signal current converted by a resistor and operates, the linearity between the input and the output of the differential amplifier is improved.

Abstract: A power saving arrangement for use in a handset unit which communicates with a base unit in response to the detection of an ID signal leading data signal, which are produced from the base unit, includes a processing circuit for receiving and processing the ID signal and data signal, and a detecting circuit, connected to the processing circuit, for detecting the ID signal and data signal. A CPU controls the power supply such that, under the first standby mode a reduced power is supplied to the processing circuit, and no power to the detecting circuit. Under the second standby mode as established when the detected level of the received signal exceeds a predetermined level, the reduced power is supplied to the processing circuit means and also to the detecting circuit means. Under the use mode as established when the detected ID signal has a predetermined pattern, full power is supplied to the processing circuit and also to the detecting circuit.

Abstract: A power saving low frequency power amplifier includes a first stage amplifier for receiving and amplifying data signal, a second stage amplifier for amplifying the output of the first stage amplifier, and a power amplifier for amplifying the output of the second amplifier. The first stage amplifier is operated in response to a driving current. The second stage amplifier receives a first idling current for obtaining a predetermined amplification, and the power amplifier receives a second idling current for obtaining a predetermined amplification. A first switching circuit is provided for making and braking paths for the first and second idling currents provided for producing a power save signal to the first switching means for braking the first switching circuit when the power save signal is present.

Abstract: A reactance circuit comprises a differential amplification circuit formed by differentially connecting the first and second transistors to each other, a load connected to a collector of the first transistor, a reactance element interposed between a base of the first transistor and a reference potential point, and a capacitor and a resistor connected in series between the collector and the base of the first transistor. A negative feedback loop to the first transistor is formed by the capacitor and the resistor. Accordingly, when the collector of the first transistor is used as an output terminal, a negative equivalent reactance is produced in the output terminal.

Abstract: Levels of a stereo sum signal and a stereo difference signal are detected by first and second level detectors (7, 9), respectively. Outputs of the first and second level detectors (7, 9) are compared with each other by a comparator (10). A voltage controlled amplifier (4) is responsive to an output of the comparator (10) for changing a level of the stereo difference signal, when a broadcasting signal including only either one of a left stereo signal and a right stereo signal is received, such that the levels of the stereo sums signal and the stereo difference signal are equal to each other.

Abstract: A stereo demodulator of a matrix system comprises: a first amplifier (23, 24, 25) for negative feedback amplification of a stereophonic composite signal, a first voltage-current converter (26) for detecting a current-form stereophonic sum signal responsive to a voltage output of the first amplifier, a non-inversion amplifier (27) for negative feedback non-inversion amplification of the stereophonic composite signal, an inversion amplifier (28) for negative feedback inversion amplification of the stereophonic composite signal, a second voltage-current converter (29, 38) for outputting a first current-form stereophonic subchannel signal responsive to a voltage output of the non-inversion amplifier (27), a third voltage-current converter (30, 39) for supplying a current-form signal stereophonic subchannel signal responsive to a voltage output from the inversion amplifier (28), a difference signal demodulator (31) for providing stereophonic difference signals of opposite phases in the form of current signals from

Abstract: An improved FMX sterophonic broadcast receiver provided with countermeasures against transient noises, which includes a level detection circuit for detecting level of a detected stereo difference signal, and a level control circuit for controlling level of an expanded stereo difference signal according to an output signal of the level detection circuit. By the above arrangement of the present invention, since it is so arranged to cause the level control circuit to function when the degree of modulation becomes large so as to control the level of the stereo difference signal to be low, a level difference is produced between the stereo sum signal and the stereo difference signal for deterioration of the stereo separation degree upon matrixing at a matrix circuit for reduction of noises accordingly.

Abstract: An FMX stereophonic receiver receives an FMX stereophonic broadcast signal which includes a stereo sum signal, an uncompressed stereo difference signal, and a compressed stereo difference signal which is formed by modulating the uncompressed stereo difference signal by a quadrature modulation and being compressed.