Abstract: A fixed length data processing apparatus has a registration holding unit holding registration information necessary to identify fixed length data that is an object of a processing commonly to transmission routes, and a data processing unit identifying whether received fixed length data is fixed length data that is an object of the processing or not on the basis of at least the registration information in the registration information holding unit to perform a data processing for fault management in the asynchronous communication on the basis of the fixed length data when identifying that the fixed length data is fixed length data that is an object of a processing correspondingly to the transmission route, thereby holding a large volume of information efficiently for identifying fixed length data to process fixed length data with a simple structure.

Abstract: In a parallel signal transmission device for converting serial signals into parallel signals at a transmitting unit to be transmitted to a receiving unit, the transmitting unit generates serial code signals from periodically latched parallel signals besides transmitted parallel signals, and adjusts phases of the parallel signals to the serial code signals by delaying the parallel signals by a predetermined delay time; and the receiving unit changes over bits of the parallel signals from the transmitting unit based on recovered clocks, detects bit shift amounts of the parallel signals after bit changeover, and performs skew adjustments of the parallel signals depending on the bit shift amounts.

Abstract: A fixed length data processing apparatus has a registration holding unit holding registration information necessary to identify fixed length data that is an object of a processing commonly to transmission routes, and a data processing unit identifying whether received fixed length data is fixed length data that is an object of the processing or not on the basis of at least the registration information in the registration information holding unit to perform a data processing for fault management in the asynchronous communication on the basis of the fixed length data when identifying that the fixed length data is fixed length data that is an object of a processing correspondingly to the transmission route, thereby holding a large volume of information efficiently for identifying fixed length data to process fixed length data with a simple structure.

Abstract: A fixed length data processing apparatus has a registration holding unit holding registration information necessary to identify fixed length data that is an object of a processing commonly to transmission routes, and a data processing unit identifying whether received fixed length data is fixed length data that is an object of the processing or not on the basis of at least the registration information in the registration information holding unit to perform a data processing for fault management in the asynchronous communication on the basis of the fixed length data when identifying that the fixed length data is fixed length data that is an object of a processing correspondingly to the transmission route, thereby holding a large volume of information efficiently for identifying fixed length data to process fixed length data with a simple structure.

Abstract: A fixed length data processing apparatus has a data processing unit receiving at least fixed length data to perform a desired data processing on the fixed length data, and an operation state monitoring process unit performing a monitoring process to monitor an operation state of an asynchronous communication on the basis of the fixed length data received by said data processing unit, thereby detecting loss or misinsertion of fixed length data such as an ATM cell or the like and monitoring a flow state in a transmission system having a high transmission rate.

Abstract: In a parallel signal transmission device for converting serial signals into parallel signals at a transmitting unit to be transmitted to a receiving unit, the transmitting unit generates serial code signals from periodically latched parallel signals besides transmitted parallel signals, and adjusts phases of the parallel signals to the serial code signals by delaying the parallel signals by a predetermined delay time; and the receiving unit changes over bits of the parallel signals from the transmitting unit based on recovered clocks, detects bit shift amounts of the parallel signals after bit changeover, and performs skew adjustments of the parallel signals depending on the bit shift amounts.