Patents by Inventor Kazuhisa Kanazawa
Kazuhisa Kanazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110310667Abstract: A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.Type: ApplicationFiled: August 29, 2011Publication date: December 22, 2011Inventors: Makoto Iwai, Kazuhisa Kanazawa, Hiroshi Nakamura, Masaki Fujiu
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Patent number: 8036038Abstract: A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.Type: GrantFiled: November 22, 2010Date of Patent: October 11, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Iwai, Kazuhisa Kanazawa, Hiroshi Nakamura, Masaki Fujiu
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Publication number: 20110063911Abstract: A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.Type: ApplicationFiled: November 22, 2010Publication date: March 17, 2011Inventors: Makoto Iwai, Kazuhisa Kanazawa, Hiroshi Nakamura, Masaki Fujiu
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Patent number: 7859901Abstract: A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.Type: GrantFiled: December 5, 2008Date of Patent: December 28, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Iwai, Kazuhisa Kanazawa, Hiroshi Nakamura, Masaki Fujiu
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Publication number: 20090185423Abstract: A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.Type: ApplicationFiled: December 5, 2008Publication date: July 23, 2009Inventors: Makoto Iwai, Kazuhisa Kanazawa, Hiroshi Nakamura, Masaki Fujiu
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Patent number: 6512702Abstract: A memory cell array is divided into left and right cell arrays, each of which includes a plurality of blocks. Data erase is sequentially controlled by an erase control circuit on the basis of an erase command flag incorporated into a command register and an address incorporated into an address register. Batch erase is carried out with respect to selected blocks of the right and left cell arrays. After data erase, a verify operation is carried out with respect to the erased blocks by retrieving the erased blocks simultaneously with respect to the right and left cell arrays in parallel. Thus, the time required to retrieve the selected blocks for the verify operation after data erase is shortened, so that the time required to carry out the whole data erase is shortened.Type: GrantFiled: March 30, 2000Date of Patent: January 28, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Toshio Yamamura, Yoshihisa Sugiura, Kazuhisa Kanazawa, Koji Sakui, Hiroshi Nakamura
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Patent number: 5450361Abstract: There is disclosed a semiconductor memory device comprising memory cells (M11 to Mmn) for storing binary data, and first reference cells (DM11 to DMm1) and second reference cells (DM12 to DMm2) corresponding to respective two storage states of the memory cell, to make comparisons between the storage state of the memory cell and the storage states of the both reference cells at first and second sense amplifiers (1, 2) to compare outputs from the both sense amplifiers at the third sense amplifier (3) to thereby detect storage data of the memory cell. Thus, there can be provided a high speed memory device which has a less number of memory cells and of a high integration structure, and which has a little possibility of an erroneous operation in reading.Type: GrantFiled: February 16, 1994Date of Patent: September 12, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Iwahashi, Hiroto Nakai, Kazuhisa Kanazawa, Isao Sato
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Patent number: 5371702Abstract: In response to a plurality of address signal input from the outside in sequence, an erase information inputting section controls an erase information holding section corresponding to the batch erase block to be erased so as to hold an erase information data. By repeating this operation in sequence, the erase information data are stored in the erase information holding sections corresponding to the plural batch erase blocks to be erased. Successively, on the basis of the erase information data stored in the erase information holding sections, block erasing sections are activated to erase all the nonvolatile memory cells of each of the corresponding blocks where the erase information data are held.Type: GrantFiled: March 5, 1993Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Hiroto Nakai, Hideo Kato, Kaoru Tokushige, Masamichi Asano, Kazuhisa Kanazawa, Toshio Yamamura
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Patent number: 5321655Abstract: There is disclosed a semiconductor memory device comprising memory cells (M11 to Mnn) for storing binary data, and first reference cells (DM11 to Dm1) and second reference cells (DM12 to DMm2) corresponding to respective two storage states of the memory cell, to make comparisons between the storage state of the memory cell and the storage states of the both reference cells at first and second sense amplifiers (1, 2) to compare outputs from the both sense amplifiers at the third sense amplifier (3) to thereby detect storage data of the memory cell. Thus, there can be provided a high speed memory device which has a less number of memory cells and of a high integration structure, and which has a little possibility of an erroneous operation in reading.Type: GrantFiled: August 24, 1993Date of Patent: June 14, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Iwahashi, Hiroto Nakai, Kazuhisa Kanazawa, Isao Sato
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Patent number: 5258958Abstract: There is disclosed a semiconductor memory device comprising memory cells (M11 to Mmn) for storing binary data, and first reference cells (DM11 to DMm1) and second reference cells (DM12 to DMm2) corresponding to respective two storage states of the memory cell, to make comparisons between the storage state of the memory cell and the storage states of the both reference cells at first and second sense amplifiers (1, 2) to compare outputs from the both sense amplifiers at the third sense amplifier (3) to thereby detect storage data of the memory cell. Thus, there can be provided a high speed memory device which has a less number of memory cells and of a high integration structure, and which has a little possibility of an erroneous operation in reading.Type: GrantFiled: December 12, 1991Date of Patent: November 2, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Iwahashi, Hiroto Nakai, Kazuhisa Kanazawa, Isao Sato
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Patent number: 5191552Abstract: In a semiconductor memory device, a first load circuit is coupled with the column lines, first dummy cells are connected to a dummy column line, a second load circuit is connected to the dummy column line, a second dummy cell is connected to the dummy column line, and a sense amplifier senses the data stored in the memory cell in accordance with a potential difference between the column line and the dummy column line. In semiconductor memory devices thus arranged, the second dummy cell is set in an on state normally. The connection of the second dummy cell with the dummy line changes a current flowing to the dummy line at the time of row line switching, thereby to hold back a rise of the reference potential at the time of the row line switching.Type: GrantFiled: May 31, 1991Date of Patent: March 2, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Hiroto Nakai, Hiroshi Iwahashi, Kazuhisa Kanazawa, Shigeru Kumagai, Isao Sato
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Patent number: 5040148Abstract: In a semiconductor memory device, a first load circuit is coupled with the column lines, first dummy cells are connected to a dummy column line, a second load circuit is connected to the dummy column line, a second dummy cell is connected to the dummy column line, and a sense amplifier senses the data stored in the memory cell in accordance with a potential difference between the column line and the dummy column line. In semiconductor memory devices thus arranged, the second dummy cell is set in an on state normally. The connection of the second dummy cell with the dummy line changes a current flowing to the dummy line at the time of row line switching, thereby to hold back a rise of the reference potential at the time of the row line switching.Type: GrantFiled: June 23, 1989Date of Patent: August 13, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Hiroto Nakai, Hiroshi Iwahashi, Kazuhisa Kanazawa, Shigeru Kumagai, Isao Sato