Abstract: An inventive semiconductor circuit device includes an N-well and a P-well. The N-well is provided with PMIS active areas surrounded by a trench isolation, and the P-well is provided with NMIS active areas surrounded by the trench isolation. The PMIS active areas are each provided with a gate of a P-channel transistor, and the NMIS active areas are each provided with a gate of an N-channel transistor. A layout is designed such that a distance Dpn between the NMIS active areas and the PMIS active areas in a Y-direction substantially becomes a fixed value. Thus, trench isolation stresses applied from the trench isolations to channel regions under the gates become uniform for respective transistors, resulting in an improvement in accuracy of circuit simulation.

Abstract: An inventive semiconductor circuit device includes an N-well and a P-well. The N-well is provided with PMIS active areas surrounded by a trench isolation, and the P-well is provided with NMIS active areas surrounded by the trench isolation. The PMIS active areas are each provided with a gate of a P-channel transistor, and the NMIS active areas are each provided with a gate of an N-channel transistor. A layout is designed such that a distance Dpn between the NMIS active areas and the PMIS active areas in a Y-direction substantially becomes a fixed value. Thus, trench isolation stresses applied from the trench isolations to channel regions under the gates become uniform for respective transistors, resulting in an improvement in accuracy of circuit simulation.

Abstract: Gates of pMISFETs which need high current driving capability are high-driving-capability gates placed in discontinuous active regions or high-driving-capability gates disposed in two-input active regions. Gate of pMISFETs which do not need high current driving capability are normal gates arranged in continuous active regions. Since the high-driving-capability gates are provided in the discontinuous active regions or the two-input active regions, pMISFETs with high driving capability is achieved by utilizing light holes created due to a lattice distortion.

Abstract: An inventive semiconductor circuit device includes an N-well and a P-well. The N-well is provided with PMIS active areas surrounded by a trench isolation, and the P-well is provided with NMIS active areas surrounded by the trench isolation. The PMIS active areas are each provided with a gate of a P-channel transistor, and the NMIS active areas are each provided with a gate of an N-channel transistor. A layout is designed such that a distance Dpn between the NMIS active areas and the PMIS active areas in a Y-direction substantially becomes a fixed value. Thus, trench isolation stresses applied from the trench isolations to channel regions under the gates become uniform for respective transistors, resulting in an improvement in accuracy of circuit simulation.

Abstract: Gates of pMISFETs which need high current driving capability are high-driving-capability gates placed in discontinuous active regions or high-driving-capability gates disposed in two-input active regions. Gate of pMISFETs which do not need high current driving capability are normal gates arranged in continuous active regions. Since the high-driving-capability gates are provided in the discontinuous active regions or the two-input active regions, pMISFETs with high driving capability is achieved by utilizing light holes created due to a lattice distortion.

Abstract: In an inventive circuit simulation method, simulation is performed utilizing a circuit simulator, based on a netlist prepared using mask layout data for a circuit, and parameters obtained from measurement data concerning the characteristic of each transistor. The parameters are extracted from the measurement data based on not only the transistor size but also a stress applied to the transistor. Therefore, the circuit simulation can be performed with precision and accuracy never before possible, in consideration of a change in the characteristic of the transistor which is caused by the stress applied thereto.