Abstract: A waveform data processing apparatus has a bus that transfers data signals representative of waveform data. A plurality of transmitting nodes transmit the data signals to the bus. A plurality of receiving nodes receive the data signals from the bus. A clock generator generates a word clock signal at each sampling period. A controller is responsive to the word clock signal for conducting a session of transferring the data signals within a sampling period, such that the transmitting nodes sequentially transmit the data signals in an order predetermined by the controller so as to avoid collision of the data signals within the sampling period, and each of the receiving nodes selectively admits a necessary one of the data signals outputted from the transmitting nodes and processes the admitted data signal within the sampling period.

Abstract: A waveform data processing apparatus has a bus that transfers data signals representative of waveform data. A plurality of transmitting nodes transmit the data signals to the bus. A plurality of receiving nodes receive the data signals from the bus. A clock generator generates a word clock signal at each sampling period. A controller is responsive to the word clock signal for conducting a session of transferring the data signals within a sampling period, such that the transmitting nodes sequentially transmit the data signals in an order predetermined by the controller so as to avoid collision of the data signals within the sampling period, and each of the receiving nodes selectively admits a necessary one of the data signals outputted from the transmitting nodes and processes the admitted data signal within the sampling period.

Abstract: A waveform data processing apparatus has a bus that transfers data signals representative of waveform data . A plurality of transmitting nodes transmit the data signals to the bus. A plurality of receiving nodes receive the data signals from the bus. A clock generator generates a word clock signal at each sampling period. A controller is responsive to the word clock signal for conducting a session of transferring the data signals within a sampling period, such that the transmitting nodes sequentially transmit the data signals in an order predetermined by the controller so as to avoid collision of the data signals within the sampling period, and each of the receiving nodes selectively admits a necessary one of the data signals outputted from the transmitting nodes and processes the admitted data signal within the sampling period.

Abstract: A waveform data processing apparatus has a bus that transfers data signals representative of waveform data. A plurality of transmitting nodes transmit the data signals to the bus. A plurality of receiving nodes receive the data signals from the bus. A clock generator generates a word clock signal at each sampling period. A controller is responsive to the word clock signal for conducting a session of transferring the data signals within a sampling period, such that the transmitting nodes sequentially transmit the data signals in an order predetermined by the controller so as to avoid collision of the data signals within the sampling period, and each of the receiving nodes selectively admits a necessary one of the data signals outputted from the transmitting nodes and processes the admitted data signal within the sampling period.

Abstract: The inventive packet transmitting apparatus transmits packets to receiving nodes located on a network, the packet containing at least one data block composed of at least one event sequence data and a timestamp added per a predetermined number of data blocks. In the packet transmitting apparatus, the packetizing section arranges the event sequence data into data blocks and adds thereto a timestamp so as to sequentially produce packets. The transmitting section sequentially transmits the packets. An error processing section operates when an error is detected during production of the packets for stopping transmission of a regular packet containing event sequence data and for generating and transmitting a special packet containing a message indicative of occurrence of the error.

Abstract: Packet transfer apparatus transmits/receives event sequence data such as audio data and music data over a fast serial network to which a plurality of devices are connected. The input section sequentially inputs event sequence data, which is sampled at a double rate by a sampling clock signal having a half period of the input clock signal.

Abstract: A packet receiving apparatus has a plurality of receiving buffers to receive packets from a plurality of transmitting nodes located on a network for reproduction of event sequence data through output channels. The packet contains at least one data block composed of at least one event sequence data and a timestamp added per a predetermined number of data blocks. In the apparatus, an unpacketizing section extracts the event sequence data and the timestamp from the packet. A writing section distributes the extracted event sequence data to the plurality of the receiving buffers for writing the event sequence data into the receiving buffers. A reading section reads out the event sequence data from the receiving buffers in accordance with the extracted timestamp. The receiving buffers are separately allotted to the plurality of the transmitting nodes and are further assigned to channels of the event sequence data contained in each packet of each transmitting node.

Abstract: A packet receiving apparatus has a plurality of receiving buffers to receive packets from a plurality of transmitting nodes located on a network for reproduction of event sequence data through output channels. The packet contains at least one data block composed of at least one event sequence data and a timestamp added per a predetermined number of data blocks. In the apparatus, an unpacketizing section extracts the event sequence data and the timestamp from the packet. A writing section distributes the extracted event sequence data to the plurality of the receiving buffers for writing the event sequence data into the receiving buffers. A reading section reads out the event sequence data from the receiving buffers in accordance with the extracted timestamp. The receiving buffers are separately allotted to the plurality of the transmitting nodes and are further assigned to channels of the event sequence data contained in each packet of each transmitting node.

Abstract: A music apparatus is constructed for processing a music tone signal in response to a clock signal at each sampling period. In the music apparatus, a clock generator generates the clock signal. A signal processor is operable in synchronization to the clock signal for time-divisionally processing a plurality of music tone signals through a plurality of channels within one sampling period. A clock controller is operative during a supply duration allocated within one sampling period for supplying the clock signal to the signal processor from the clock generator to thereby operate the signal processor, and is operative during other than the supply duration within one sampling period for stopping the supplying of the clock signal to the signal processor to thereby suspend the signal processor.

Abstract: A packet receiving apparatus has a plurality of receiving buffers to receive packets from a plurality of transmitting nodes located on a network for reproduction of event sequence data through output channels. The packet contains at least one data block composed of at least one event sequence data and a timestamp added per a predetermined number of data blocks. In the apparatus, an unpacketizing section extracts the event sequence data and the timestamp from the packet. A writing section distributes the extracted event sequence data to the plurality of the receiving buffers for writing the event sequence data into the receiving buffers. A reading section reads out the event sequence data from the receiving buffers in accordance with the extracted timestamp. The receiving buffers are separately allotted to the plurality of the transmitting nodes and are further assigned to channels of the event sequence data contained in each packet of each transmitting node.

Abstract: A waveform data processing apparatus has a bus that transfers data signals representative of waveform data. A plurality of transmitting nodes transmit the data signals to the bus. A plurality of receiving nodes receive the data signals from the bus. A clock generator generates a word clock signal at each sampling period. A controller is responsive to the word clock signal for conducting a session of transferring the data signals within a sampling period, such that the transmitting nodes sequentially transmit the data signals in an order predetermined by the controller so as to avoid collision of the data signals within the sampling period, and each of the receiving nodes selectively admits a necessary one of the data signals outputted from the transmitting nodes and processes the admitted data signal within the sampling period.

Abstract: A music apparatus is constructed for processing a music tone signal in response to a clock signal at each sampling period. In the music apparatus, a clock generator generates the clock signal. A signal processor is operable in synchronization to the clock signal for time-divisionally processing a plurality of music tone signals through a plurality of channels within one sampling period. A clock controller is operative during a supply duration allocated within one sampling period for supplying the clock signal to the signal processor from the clock generator to thereby operate the signal processor, and is operative during other than the supply duration within one sampling period for stopping the supplying of the clock signal to the signal processor to thereby suspend the signal processor.

Abstract: A music apparatus is constructed for processing a music tone signal in response to a clock signal at each sampling period. In the music apparatus, a clock generator generates the clock signal. A signal processor is operable in synchronization to the clock signal for time-divisionally processing a plurality of music tone signals through a plurality of channels within one sampling period. A clock controller is operative during a supply duration allocated within one sampling period for supplying the clock signal to the signal processor from the clock generator to thereby operate the signal processor, and is operative during other than the supply duration within one sampling period for stopping the supplying of the clock signal to the signal processor to thereby suspend the signal processor.

Abstract: A mixing apparatus is constructed for mixing input voice signals with each other to produce output voice signals. In the mixing apparatus, a generator has a predetermined number of internal channels for internally generating the predetermined number of input voice signals at each sample period divided into the predetermined number of timeslots to accommodate the predetermined number of the input voice signals within each sample period. A converter converts division of the sample period so as to increase a total number of the timeslots within each sample period, and distributes the predetermined number of the input voice signals to the increased number of the timeslots so as to create an extra number of free timeslots within each sample period. An interface can receive the extra number of input voice signals provided from the extra number of external channels of an external signal source disposed separately from the generator.

Abstract: A music apparatus is constructed for processing a music tone signal in response to a clock signal at each sampling period. In the music apparatus, a clock generator generates the clock signal. A signal processor is operable in synchronization to the clock signal for time-divisionally processing a plurality of music tone signals through a plurality of channels within one sampling period. A clock controller is operative during a supply duration allocated within one sampling period for supplying the clock signal to the signal processor from the clock generator to thereby operate the signal processor, and is operative during other than the supply duration within one sampling period for stopping the supplying of the clock signal to the signal processor to thereby suspend the signal processor.

Abstract: A signal processing apparatus executes a plurality of microprograms stored in a microprogram memory device in a time-sharing manner, so as to perform arithmetic operations on a digital signal entered by a signal input device. A delay memory device that delays the digital signal. The delay memory device has a plurality of delay areas that are independently provided for the respective microprograms, such that each of the microprograms that is being executed uses a corresponding one of the plurality of delay areas so as to delay the digital signal, and a common area that can be accessed by all of the microprograms. As a result, data such as tables for use in common by the plurality of microprograms can be stored, and the stored data can be easily used by each microprogram, without making the system complicated or increasing the cost of the apparatus.

Abstract: A sound effect imparting apparatus, which is employed in the electronic musical instrument in order to impart a variety of sound effects to the musical tones in a variety of manners, is mainly configured by an effect program memory, a sound-effect operation portion, a mixer and a mixing information supply portion. The effect program memory stores a plurality of effect programs, respectively corresponding to a plurality of sound effects to be imparted to musical tone data, in advance. The sound-effect operation portion performs arithmetic operations and/or logical operations on its input data in accordance with the effect programs read from the effect program memory, thus imparting desired sound effects to the musical tone data. The mixer receives the musical tone data, given from an external device, and operation data, outputted from the sound-effect operation portion, representing the musical tone data to which the sound effects have been imparted.

Abstract: A signal processor executes a plurality of microprograms to perform delaying processing and various arithmetic computation processings of digital signals input thereto. The signal processor has a storage area divided into a plurality of divided areas corresponding, respectively, to the microprograms. The write and read of the divided areas are controlled. When an instruction for changing at least one of the microprograms is given, the write and read of the digital signals are controlled such that at least one of the digital signals stored in at least one of the divided areas corresponds to the at least one microprogram is cleared without clearing the others of the digital signals stored in the others of the divided areas.

Abstract: A music apparatus is constructed for processing a music tone signal in response to a clock signal at each sampling period. In the music apparatus, a clock generator generates the clock signal. A signal processor is operable in synchronization to the clock signal for time-divisionally processing a plurality of music tone signals through a plurality of channels within one sampling period. A clock controller is operative during a supply duration allocated within one sampling period for supplying the clock signal to the signal processor from the clock generator to thereby operate the signal processor, and is operative during other than the supply duration within one sampling period for stopping the supplying of the clock signal to the signal processor to thereby suspend the signal processor.

Abstract: A waveform data processing apparatus has a bus that transfers data signals representative of waveform data. A plurality of transmitting nodes transmit the data signals to the bus. A plurality of receiving nodes receive the data signals from the bus. A clock generator generates a word clock signal at each sampling period. A controller is responsive to the word clock signal for conducting a session of transferring the data signals within a sampling period, such that the transmitting nodes sequentially transmit the data signals in an order predetermined by the controller so as to avoid collision of the data signals within the sampling period, and each of the receiving nodes selectively admits a necessary one of the data signals outputted from the transmitting nodes and processes the admitted data signal within the sampling period.