Abstract: A burst length discriminating circuit for use in a synchronous semiconductor memory with a burst mode, which receives the three least significant address signals of an address, includes an inverter receiving the address IA2, a first D-type flipflop or latch for latching and holding the address signal IA0, a second D-latch for latching and holding the address signal IA1, and a third D-latch for latching and holding an output of the inverter. A decoder receives respective outputs of the first to third D-latches for selectively activating a burst length discrimination signal determined by a logical combination of the address signals IA0, IA1 and IA2, and activates an any burst length discrimination signal other than a burst length discrimination signal indicating the full page, when the outputs of all the first to third D-latches are at the high level.

Abstract: A burst length discriminating circuit for use in a synchronous semiconductor memory with a burst mode, which receives the three least significant address signals IA0, IA1 and IA2 of an address, includes an inverter receiving the address signal IA2, a first D-latch for latching and holding the address signal IA0, a second D-latch for latching and holding the address signal IA1, and a third D-latch for latching and holding an output of the inverter. A decoder receives respective outputs of the first to third D-latches for selectively activating a burst length discrimination signal determined by a logical combination of the address signals IA0, IA1 and IA2, but for activating any burst length discrimination signal other than a burst length discrimination signal indicating the full page, when the outputs of all the first to third D-latches are at the high level.