Abstract: Upon designing a standard cell type semiconductor chip, there are prepared a plurality of types of standard cells and a plurality of types of yield improvement standard cells having the same function as the standard cells and having a layout which is changed to improve yield. A priority order list to be used upon replacing the plurality of types of first standard cells is generated. Automatic placement is performed by using the plurality of types of first standard cells. A certain type of a first standard cell is selected from the plurality of types of first standard cells according to a priority order in the generated list. The selected type of a first standard cell is replaced with a corresponding type of a second standard cell.

Abstract: Upon designing a standard cell type semiconductor chip, there are prepared a plurality of types of standard cells and a plurality of types of yield improvement standard cells having the same function as the standard cells and having a layout which is changed to improve yield. A priority order list to be used upon replacing the plurality of types of first standard cells is generated. Automatic placement is performed by using the plurality of types of first standard cells. A certain type of a first standard cell is selected from the plurality of types of first standard cells according to a priority order in the generated list. The selected type of a first standard cell is replaced with a corresponding type of a second standard cell.

Abstract: An ESD protection circuit comprising a first pad, a second pad, and a clamp circuit. The first pad is used as an external connection terminal to be connected to a semiconductor integrated circuit. The second pad is used as an external connection terminal to be connected to the semiconductor integrated circuit. The clamp circuit is connected between the first pad and the second pad. The ESD protecting circuit further comprises a control circuit. The control circuit controls the clamp circuit, rendering the same conducting or non-conducting.

Abstract: An ESD protection circuit comprising a first pad, a second pad, and a clamp circuit. The first pad is used as an external connection terminal to be connected to a semiconductor integrated circuit. The second pad is used as an external connection terminal to be connected to the semiconductor integrated circuit. The clamp circuit is connected between the first pad and the second pad. The ESD protecting circuit further comprises a control circuit. The control circuit controls the clamp circuit, rendering the same conducting or non-conducting.

Abstract: Provided is a bonding pad structure of a semiconductor device that is unlikely to give rise to an open failure caused by the electromigration in the pad wiring portion. The input-output signal current and the power supply current of the semiconductor chip flowing through the bonding wire is branched to flow from the bonding region into the underlying metal wiring through via metals. A via metal connecting region consisting of the underlying metal wiring layer is formed in the lower peripheral region of the bonding region so as to allow the current flowing from the bonding wire to be branched from the upper via metal connecting region formed in the bonding pad region into the underlying metal wiring connected to the underlying via metal connecting region through a plurality of via metals so as to moderate the current concentration and, thus, to avoid the open failure caused by the electromigration.

Abstract: Provided is a bonding pad structure of a semiconductor device that is unlikely to give rise to an open failure caused by the electromigration in the pad wiring portion. The input-output signal current and the power supply current of the semiconductor chip flowing through the bonding wire is branched to flow from the bonding region into the underlying metal wiring through via metals. A via metal connecting region consisting of the underlying metal wiring layer is formed in the lower peripheral region of the bonding region so as to allow the current flowing from the bonding wire to be branched from the upper via metal connecting region formed in the bonding pad region into the underlying metal wiring connected to the underlying via metal connecting region through a plurality of via metals so as to moderate the current concentration and, thus, to avoid the open failure caused by the electromigration.

Abstract: A semiconductor memory device having information data storing cells and error correction data storing memory cells. When information data is inputted, error correction data related to the information data is formed. In a usual use, the information data and the error correction data are stored in the corresponding memory cells. An external test signal, inputted as the information data, can be stored in the error correction data storing memory cells by a write control signal. In a usual use, the information data stored in the information data storing cells are outputted, as they are or corrected if erroneous. The test signal stored in the error correction data storing memory can be outputted by an output control signal.

Abstract: An oscillator including a CMOS inverter, a feedback reactance connected between the input and output terminals of the CMOS inverter and a CMOS transfer gate connected as a feedback resistor between the input and output terminals of the CMOS inverter, a power source terminal section to which an external voltage is applied, and a power control unit for converting the external voltage to a first internal voltage which is supplied as a power source voltage to the CMOS inverter. The power control unit converts the external voltage to a second internal voltage independently from the first internal voltage and supplies the second internal voltage as a gate control voltage to the CMOS transfer gate.

Abstract: A first node is connected to an external power source via a switch. A second node is connected to an internal power source whose voltage is lower than that of the external power source. The first and second nodes are connected to an output node via first and second MOSFET switches. The output node is connected to a semiconductor circuit. The potentials at the first and second nodes are compared with each other by a voltage comparator connected between the output node and ground. A MOSFET is quickly turned on and off in response to the potential at the first node.