Patents by Inventor Kazuhisa Shimazu

Kazuhisa Shimazu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit verification method, verification apparatus, and verification program
    Publication number: 20060117283
    Abstract: A verification method of an integrated circuit including an input/output buffer placed in a periphery of a semiconductor device and an internal circuit. The verification method stores physical information on routing of the input/output buffer into a library of the input/output buffer and verifies a placement of the input/output buffer based on the physical information.
    Type: Application
    Filed: November 22, 2005
    Publication date: June 1, 2006
    Inventors: Tetsuya Katou, Makoto Nonaka, Hideyuki Okabe, Kazuhisa Shimazu