Abstract: A switching output circuit is provided that enables an accurate control of output power. To achieve the objective, a switching output circuit according to an exemplary aspect of the present invention includes eight switching means, two electric storage means, and a control means, wherein the control means controls the switching means and switches a conduction state and a non-conduction state, by which the power supplied from a direct-current power supply is switched and supplied to an inductive load.

Abstract: A pulsed discharge device according to an exemplary aspect of the present invention includes a controller configured to determine an interruption time to a discharge time based on a predetermined time ratio between the discharge time and the interruption time when performing a pulsed discharge to repeat alternately a discharge and a pause in discharging of a chemical battery.

Abstract: A pulsed discharge device according to an exemplary aspect of the present invention includes a controller configured to determine an interruption time to a discharge time based on a predetermined time ratio between the discharge time and the interruption time when performing a pulsed discharge to repeat alternately a discharge and a pause in discharging of a chemical battery.

Abstract: A switching output circuit is provided that enables an accurate control of output power. To achieve the objective, a switching output circuit according to an exemplary aspect of the present invention includes eight switching means, two electric storage means, and a control means, wherein the control means controls the switching means and switches a conduction state and a non-conduction state, by which the power supplied from a direct-current power supply is switched and supplied to an inductive load.

Abstract: A lithium ion secondary battery system allowing a high power efficiency and large effective capacity is provided. The system includes an external power source for charging a lithium ion secondary battery, and a controller for switching output modes including a continuous discharge mode, in which electric power is continuously supplied from the lithium ion secondary battery to the load, and a pulsed charge and discharge mode, in which pulsed electric power is supplied from the lithium ion secondary battery to the load, and pulsed electric power is supplied from the external power source to charge the lithium ion secondary battery during a low-level pulsed discharge period(s), which are periods during which electric power is not supplied to the load, wherein the controller switches the output modes to the pulsed charge and discharge mode when the lithium ion secondary battery has a voltage lower than a predetermined upper switching voltage.

Abstract: An abnormality diagnosis device includes: a measurement unit (cell voltage measurement unit (202)) for measuring the state of a device to be diagnosed (battery cell); a first abnormality determination unit (overvoltage and over-discharge determination unit (203)) for determining the abnormality of the device to be diagnosed on the basis of the measurement results; and a second abnormality determination unit (main processing unit (301)) for similarly determining the abnormality of the device to be diagnosed on the basis of the measurement results. The measurement unit (202) and the first abnormality determination unit (203) are provided on a first substrate (cell state measurement unit (101)), while the second abnormality determination unit (301) is provided on a second substrate (cell state calculation unit) different from the first substrate, so that the failure rate due to a common failure factor (substrate) is reduced.

Abstract: A clock data recovery circuit includes: a demodulation filter that receives a transmission signal transmitted by two orthogonal carrier waves having I and Q phases and executes demodulation to obtain a demodulated wave having an phase and a demodulated wave having a Q phase from the transmission signal; a first determination circuit that determines whether an absolute value of one of the two demodulated waves is greater than an eye opening maximum value at an ideal clock phase of the transmission signal; a second determination circuit that determines whether the one demodulated wave is greater than zero; a third determination circuit that determines whether the other one of the two demodulated waves is greater than zero; and a phase comparison unit that detects whether a phase of a clock signal included in the transmission signal is leading a phase of a data signal included in the transmission signal, based on determination results obtained by the first to third determination circuits.

Abstract: A decision feedback equalizer is provided for correcting ISI on a first postcursor without using received decision data of a preceding bit. The decision feedback equalizer includes an amplifying circuit that is to be supplied with received data, a duobinary signal decision device for determining an output signal from the amplifying circuit, the duobinary signal decision device including a flip-flop, a shift register for successively shifting a decision result held by the flip-flop, and a plurality of current control blocks that are to be supplied with respective output signals from the shift register, and feeding back output signals to an output terminal of the amplifier to control the potential thereof.

Abstract: A waveform equalization circuit includes: a decision feedback equalization unit that feeds back and equalizes an input signal; a clock phase adjustment unit that adjusts a clock phase of a signal equalized by the decision feedback equalization unit based on a signal determined with a prescribed potential as a threshold; and a duo-binary decoder that encodes, into a duo-binary signal, the signal determined with the prescribed potential as a threshold based on a clock adjusted by the clock phase adjustment unit from the signal equalized by the decision feedback equalization unit; wherein the equalized signal is generated by adding the duo-binary signal encoded by the duo-binary decoder to the input signal. A first post-tap of the input signal is equalized by the clock phase adjustment unit without feedback equalization by the decision feedback equalization unit. Second and subsequent post-taps of the input signal are fed back and equalized by the decision feedback equalization unit.

Abstract: Disclosed is an apparatus including an odd data receiving unit that receives an input signal, an even data receiving unit that also receives the input signal, and a pattern filter. The odd data receiving unit samples a half-rate DFE equalized signal with an odd data timing clock to output data decision data. The even data receiving unit samples the half-rate DFE equalized signal with an even data timing clock having the phase shifted by 180 degrees from the odd data timing clock to output data decision data. The pattern filter selects one of the edge decision data sampled at the odd edge timing and at the even edge timing in response to the value of a data pattern of three consecutive bits obtained from the data decision data sampled at the odd and even data timings.

Abstract: A clock data recovery circuit includes: a demodulation filter that receives a transmission signal transmitted by two orthogonal carrier waves having I and Q phases and executes demodulation to obtain a demodulated wave having an phase and a demodulated wave having a Q phase from the transmission signal; a first determination circuit that determines whether an absolute value of one of the two demodulated waves is greater than an eye opening maximum value at an ideal clock phase of the transmission signal; a second determination circuit that determines whether the one demodulated wave is greater than zero; a third determination circuit that determines whether the other one of the two demodulated waves is greater than zero; and a phase comparison unit that detects whether a phase of a clock signal included in the transmission signal is leading a phase of a data signal included in the transmission signal, based on determination results obtained by the first to third determination circuits.

Abstract: A common mode of a waveform of a duobinary transmission signal (IN) is set to 0 and the size of a data eye is set to Veye; and reference potentials Vref_H and Vref_L are set to the following values: Veye/?{square root over (3)}?Vref—H?Veye/?{square root over (2)}??(1) ?Veye/?{square root over (2)}?Vref—L??Veye/?{square root over (3)}??(2) More particularly, effect becomes remarkable by setting the reference potentials Vref_H and Vref_L to central values in ranges shown in Equations (1) and (2), respectively. In the central values, fluctuation (jitter) of transition data becomes the smallest, and a jitter characteristic of a reproducing clock becomes the best. Consequently, a clock reproducing apparatus in which a received clock from duobinary transmission data is reproduced with high accuracy is provide.

Abstract: A waveform equalization circuit includes: a decision feedback equalization unit that feeds back and equalizes an input signal; a clock phase adjustment unit that adjusts a clock phase of a signal equalized by the decision feedback equalization unit based on a signal determined with a prescribed potential as a threshold; and a duo-binary decoder that encodes, into a duo-binary signal, the signal determined with the prescribed potential as a threshold based on a clock adjusted by the clock phase adjustment unit from the signal equalized by the decision feedback equalization unit; wherein the equalized signal is generated by adding the duo-binary signal encoded by the duo-binary decoder to the input signal. A first post-tap of the input signal is equalized by the clock phase adjustment unit without feedback equalization by the decision feedback equalization unit. Second and subsequent post-taps of the input signal are fed back and equalized by the decision feedback equalization unit.

Abstract: Precoded data transmitted from transmitting apparatus (101) is received by receiving apparatus (102) as duobinary data being ternary data via transmission path (103), and the duobinary data is converted into differential data being binary data by absolute value converter (121) comprising an AND gate and an OR gate.

Abstract: A data transmission system is made up from: a transmission circuit (100) for generating and transmitting a data sequence in which the abundance ratio of each value for each prescribed data length is fixed, and a reception circuit (101) for, based on the abundance ratio of each value of a data sequence transmitted from the transmission circuit (100), correcting the offset voltage of a signal detection circuit (3) that detects values of the data sequence.

Abstract: A common mode of a waveform of a duobinary transmission signal (IN) is set to 0 and the size of a data eye is set to Veye; and reference potentials Vref_H and Vref_L are set to the following values: Veye/?{square root over (3)}?Vref—H?Veye/?{square root over (2)}??(1) ?Veye/?{square root over (2)}?Vref—L??Veye/?{square root over (3)}??(2) More particularly, effect becomes remarkable by setting the reference potentials Vref_H and Vref_L to central values in ranges shown in Equations (1) and (2), respectively. In the central values, fluctuation (jitter) of transition data becomes the smallest, and a jitter characteristic of a reproducing clock becomes the best. Consequently, a clock reproducing apparatus in which a received clock from duobinary transmission data is reproduced with high accuracy is provide.

Abstract: A decision feedback equalizer is provided for correcting ISI on a first postcursor without using received decision data of a preceding bit. The decision feedback equalizer includes an amplifying circuit that is to be supplied with received data, a duobinary signal decision device for determining an output signal from the amplifying circuit, the duobinary signal decision device including a flip-flop, a shift register for successively shifting a decision result held by the flip-flop, and a plurality of current control blocks that are to be supplied with respective output signals from the shift register, and feeding back output signals to an output terminal of the amplifier to control the potential thereof.

Abstract: A data receiving device comprises amplifying circuit 41 that amplifies received duobinary data with a given gain into an output signal, offset canceler 56, 57 that cancel an offset of the output signal from amplifying circuit 41, data determiner 43, 44 that sample the output signal from amplifying circuit 41 based on a first reference voltage and a second reference voltage which is of a lower level than the first reference voltage to determine which one of three levels of the duobinary data the received duobinary data have.

Abstract: Disclosed is an apparatus including an odd data receiving unit that receives an input signal, an even data receiving unit that also receives the input signal, and a pattern filter. The odd data receiving unit samples a half-rate DFE equalized signal with an odd data timing clock to output data decision data. The odd data receiving unit also samples both the half-rate DFE equalized signal and a non-half-rate DFE equalized signal with an odd edge timing clock having the phase shifted by 90 degrees from the odd data timing clock to output resulting edge decision data. The even data receiving unit samples the half-rate DFE equalized signal with an even data timing clock having the phase shifted by 180 degrees from the odd data timing clock to output data decision data.

Abstract: A data transmission system is made up from: a transmission circuit (100) for generating and transmitting a data sequence in which the abundance ratio of each value for each prescribed data length is fixed, and a reception circuit (101) for, based on the abundance ratio of each value of a data sequence transmitted from the transmission circuit (100), correcting the offset voltage of a signal detection circuit (3) that detects values of the data sequence.